Issued Patents All Time
Showing 1–25 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9369175 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ming-Ta Lei, Chuen-Jye Lin | 2016-06-14 |
| 9136246 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Mou-Shiung Lin, Jin-Yuan Lee | 2015-09-15 |
| 9030029 | Chip package with die and substrate | Mou-Shiung Lin, Jin-Yuan Lee | 2015-05-12 |
| 9018774 | Chip package | Jin-Yuan Lee, Mou-Shiung Lin | 2015-04-28 |
| 8912666 | Structure and manufacturing method of chip scale package | Jin-Yuan Lee, Mou-Shiung Lin | 2014-12-16 |
| 8901733 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin | 2014-12-02 |
| 8835221 | Integrated chip package structure using ceramic substrate and method of manufacturing the same | Jin-Yaun Lee, Mou-Shiung Lin | 2014-09-16 |
| 8748227 | Method of fabricating chip package | Jin-Yuan Lee, Mou-Shiung Lin | 2014-06-10 |
| 8546947 | Chip structure and process for forming the same | Jin-Yuan Lee, Mou-Shiung Lin | 2013-10-01 |
| 8535976 | Method for fabricating chip package with die and substrate | Jin-Yuan Lee, Mou-Shiung Lin | 2013-09-17 |
| 8492870 | Semiconductor package with interconnect layers | Mou-Shiung Lin, Jin-Yuan Lee | 2013-07-23 |
| 8481418 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ming-Ta Lei, Chuen-Jye Lin | 2013-07-09 |
| 8471361 | Integrated chip package structure using organic substrate and method of manufacturing the same | Mou-Shiung Lin, Jin-Yuan Lee | 2013-06-25 |
| 8426982 | Structure and manufacturing method of chip scale package | Jin-Yuan Lee, Mou-Shiung Lin | 2013-04-23 |
| 8368213 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Mou-Shiung Lin | 2013-02-05 |
| 8368204 | Chip structure and process for forming the same | Mou-Shiung Lin, Jin-Yuan Lee | 2013-02-05 |
| 8362171 | Norbornene monomers with an epoxy group and polymer material thereof | Der-Jang Liaw | 2013-01-29 |
| RE43674 | Post passivation metal scheme for high-performance integrated circuit devices | Mou-Shiung Lin, Jin-Yuan Lee, Ming-Ta Lei | 2012-09-18 |
| 8211791 | Method for fabricating circuitry component | Mou-Shiung Lin, Jin-Yuan Lee | 2012-07-03 |
| 8178967 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ming-Ta Lei, Chuen-Jye Lin | 2012-05-15 |
| 8119446 | Integrated chip package structure using metal substrate and method of manufacturing the same | Mou-Shiung Lin, Jin-Yuan Lee | 2012-02-21 |
| 8072070 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Mou-Shiung Lin | 2011-12-06 |
| 8008776 | Chip structure and process for forming the same | Jin-Yuan Lee, Mou-Shiung Lin | 2011-08-30 |
| 7977763 | Chip package with die and substrate | Mou-Shiung Lin, Jin-Yuan Lee | 2011-07-12 |
| 7932603 | Chip structure and process for forming the same | Jin-Yuan Lee, Mou-Shiung Lin | 2011-04-26 |