Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7335704 | Functional norbornenes and polymeric derivatives and fabrication thereof | Der-Jang Liaw, Jing-Yang Ju, Jiun-Tyng Liaw | 2008-02-26 |
| 7309920 | Chip structure and process for forming the same | Mou-Shiung Lin, Jin-Yuan Lee | 2007-12-18 |
| 7297614 | Method for fabricating circuitry component | Jin-Yuan Lee, Mou-Shiung Lin | 2007-11-20 |
| 7271033 | Method for fabricating chip package | Mou-Shiung Lin, Jin-Yuan Lee | 2007-09-18 |
| 7271223 | Norbomene compounds with cross-linkable groups and their derivatives | Der-Jang Liaw | 2007-09-18 |
| 7271230 | Norbornene compounds with cross-linkable groups and their derivatives | Der-Jang Liaw | 2007-09-18 |
| 7205359 | Functional norbornenes as initiators for radical polymerization, their polymeric derivatives and a process for producing the same | Der-Jang Liaw | 2007-04-17 |
| 7132565 | Norbornene compounds with cross-linkable groups and their derivatives | Der-Jang Liaw, Shou-Mau Hong, Ming-Hung Huang | 2006-11-07 |
| 6936531 | Process of fabricating a chip structure | Mou-Shiung Lin, Jin-Yuan Lee | 2005-08-30 |
| 6917119 | Low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ming-Ta Lei, Chuen-Jye Lin | 2005-07-12 |
| 6818545 | Low fabrication cost, fine pitch and high reliability solder bump | Jin-Yuan Lee, Mou-Shiung Lin | 2004-11-16 |
| 6815324 | Reliable metal bumps on top of I/O pads after removal of test probe marks | Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin | 2004-11-09 |
| 6800941 | Integrated chip package structure using ceramic substrate and method of manufacturing the same | Jin-Yuan Lee, Mou-Shiung Lin | 2004-10-05 |
| 6798073 | Chip structure and process for forming the same | Mou-Shiung Lin, Jin-Yuan Lee | 2004-09-28 |
| 6762115 | Chip structure and process for forming the same | Mou-Shiung Lin, Jin-Yuan Lee | 2004-07-13 |
| 6756295 | Chip structure and process for forming the same | Mou-Shiung Lin, Jin-Yuan Lee | 2004-06-29 |
| 6746898 | Integrated chip package structure using silicon substrate and method of manufacturing the same | Mou-Shiung Lin, Jin-Yuan Lee | 2004-06-08 |
| 6700162 | Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip | Mou-Shiung Lin, Jin-Yuan Lee | 2004-03-02 |
| 6673698 | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers | Mou-Shiung Lin, Jin-Yuan Lee | 2004-01-06 |
| 6649509 | Post passivation metal scheme for high-performance integrated circuit devices | Mou-Shiung Lin, Ming-Ta Lei, Jin-Yuan Lee | 2003-11-18 |
| 6642136 | Method of making a low fabrication cost, high performance, high reliability chip scale package | Jin-Yuan Lee, Ming-Ta Lei, Chuen-Jye Lin | 2003-11-04 |
| 6605528 | Post passivation metal scheme for high-performance integrated circuit devices | Mou-Shiung Lin, Ming-Ta Lei, Jin-Yuan Lee | 2003-08-12 |
| 6495912 | Structure of ceramic package with integrated passive devices | Mou-Shiung Lin, Jin-Yuan Lee | 2002-12-17 |
| 5755913 | Adhesive-free adhesion between polymer surfaces | Der-Jang Liaw, En-Tang Kang, Kuang Lee Tan, Koon Gee Neoh | 1998-05-26 |