Issued Patents All Time
Showing 101–125 of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6500727 | Silicon shallow trench etching with round top corner by photoresist-free process | Cheng-Ku Chen, Fang Chen | 2002-12-31 |
| 6497993 | In situ dry etching procedure to form a borderless contact hole | Yuan-Hunh Chiu, Chia-Shiung Tsai, Chu-Yun Fu | 2002-12-24 |
| 6498067 | Integrated approach for controlling top dielectric loss during spacer etching | Baw-Ching Perng, Ming-Huang Tsai, Ju-Wang Hsu | 2002-12-24 |
| 6479403 | Method to pattern polysilicon gates with high-k material gate dielectric | Ming-Huan Tsei, Baw-Ching Perng | 2002-11-12 |
| 6472335 | Methods of adhesion promoter between low-K layer and underlying insulating layer | Chia-Shiung Tsai, Yao-Yi Cheng | 2002-10-29 |
| 6444566 | Method of making borderless contact having a sion buffer layer | Ming-Huan Tsai, Jyh-Huei Chen, Chu-Yun Fu | 2002-09-03 |
| 6440863 | Plasma etch method for forming patterned oxygen containing plasma etchable layer | Chia-Shiun Tsai, Chao-Cheng Chen | 2002-08-27 |
| 6436841 | Selectivity oxide-to-oxynitride etch process using a fluorine containing gas, an inert gas and a weak oxidant | Ming-Huan Tsai, Bao-Ching Pen, Mei-Ru Kuo | 2002-08-20 |
| 6410424 | Process flow to optimize profile of ultra small size photo resist free contact | Ming-Huan Tsai, Chung-Long Chang, Chii-Ming Wu | 2002-06-25 |
| 6407002 | Partial resist free approach in contact etch to improve W-filling | Li-Te Lin, Yuan-Hung Chiu, Ming-Huan Tsai | 2002-06-18 |
| 6399515 | Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity | Chia-Shiung Tsai | 2002-06-04 |
| 6399483 | Method for improving faceting effect in dual damascene process | Jen-Cheng Liu, Ming-Huei Lui, Chia-Shiung Tsai | 2002-06-04 |
| 6333271 | Multi-step plasma etch method for plasma etch processing a microelectronic layer | Yuan-Hung Chiu, Yu-I Wang, Huan-Just Lin | 2001-12-25 |
| 6331480 | Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material | Chia-Shiung Tsai, Yao-Yi Cheng | 2001-12-18 |
| 6326296 | Method of forming dual damascene structure with improved contact/via edge integrity | Chia-Shiung Tsai | 2001-12-04 |
| 6319822 | Process for forming an integrated contact or via | Chao-Cheng Chen, Chia-Shiung Tsai, Shau-Lin Shue | 2001-11-20 |
| 6265317 | Top corner rounding for shallow trench isolation | Hsien-Kuang Chiu, Fang Chen | 2001-07-24 |
| 6242350 | Post gate etch cleaning process for self-aligned gate mosfets | Chia-Shiung Tsai, Yuan-Chang Huang | 2001-06-05 |
| 6235440 | Method to control gate CD | Huan-Just Lin, Fang Chen | 2001-05-22 |
| 6194128 | Method of dual damascene etching | Chao-Cheng Chen, Chia-Shiung Tsai | 2001-02-27 |
| 6183937 | Post photodevelopment isotropic radiation treatment method for forming patterned photoresist layer with attenuated linewidth | Chia-Shiung Tsai | 2001-02-06 |
| 6174818 | Method of patterning narrow gate electrode | Huan-Just Lin, Hung-Chang Hsieh, Chu-Yun Fu, Ying-Ying Wang, Chia-Shiung Tsai +1 more | 2001-01-16 |
| 6165881 | Method of forming salicide poly gate with thin gate oxide and ultra narrow gate width | Chia-Shiung Tsai | 2000-12-26 |
| 6156629 | Method for patterning a polysilicon gate in deep submicron technology | Yuan-Chang Huang | 2000-12-05 |
| 6129091 | Method for cleaning silicon wafers with deep trenches | Kuei-Ying Lee, Chia-Shiung Tsai | 2000-10-10 |