Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12317570 | Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance | Kuo-Chiang Tsai, Hsin-Huang Lin | 2025-05-27 |
| 12243826 | Method for manufacturing semiconductor structure having raised via contacts | Kuo-Chiang Tsai, Jye-Yen Cheng | 2025-03-04 |
| 12154957 | Semiconductor devices and methods of manufacture | Kuo-Chiang Tsai | 2024-11-26 |
| 12154856 | Methods of manufacturing via structures on source/drain contacts | Kuo-Chiang Tsai, Yi-Ju Chen | 2024-11-26 |
| 12148797 | Gate air spacer protection during source/drain via hole etching | Kuo-Chiang Tsai | 2024-11-19 |
| 12074218 | Contact structure with insulating cap | Kuo-Chiang Tsai, Fu-Hsiang Su, Yi-Ju Chen | 2024-08-27 |
| 12046646 | Contact and via structures | Kuo-Chiang Tsai | 2024-07-23 |
| 12040225 | Insulating cap on contact structure | Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu | 2024-07-16 |
| 11955380 | Conductive element for semiconductor devices | Kuo-Chiang Tsai | 2024-04-09 |
| 11837663 | Via structure with low resistivity and method for forming the same | Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang | 2023-12-05 |
| 11784218 | Gate air spacer protection during source/drain via hole etching | Kuo-Chiang Tsai | 2023-10-10 |
| 11626495 | Protective liner for source/drain contact to prevent electrical bridging while minimizing resistance | Kuo-Chiang Tsai, Hsin-Huang Lin | 2023-04-11 |
| 11569362 | Semiconductor device and a method for fabricating the same | Chia-Ming Hsu, Pei-Yu Chou, Chih-Pin Tsao, Kuang-Yuan Hsu | 2023-01-31 |
| 11545432 | Semiconductor device with source and drain vias having different sizes | Kuo-Chiang Tsai, Yi-Ju Chen | 2023-01-03 |
| 11508616 | Electrical connection for semiconductor devices | Kuo-Chiang Tsai | 2022-11-22 |
| 11424188 | Methods of fabricating integrated circuit devices having raised via contacts | Kuo-Chiang Tsai, Jye-Yen Cheng | 2022-08-23 |
| 11393717 | Insulating cap on contact structure and method for forming the same | Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu | 2022-07-19 |
| 11139203 | Using mask layers to facilitate the formation of self-aligned contacts and vias | Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen | 2021-10-05 |
| 11081585 | Via structure with low resistivity and method for forming the same | Kuo-Chiang Tsai, Fu-Hsiang Su, Ke-Jing Yu, Chih-Hong Hwang | 2021-08-03 |
| 11069784 | Semiconductor device and method of manufacture | Kuo-Chiang Tsai | 2021-07-20 |
| 11018057 | Semiconductor devices | Fu-Hsiang Su, Kuo-Chiang Tsai, Ke-Jing Yu | 2021-05-25 |
| 11011636 | Fin field effect transistor (FinFET) device structure with hard mask layer over gate structure and method for forming the same | Cheng-Han Wu, Yu-Ho Chiang, Jhon Jhy Liaw | 2021-05-18 |
| 10950497 | Electrical connection for semiconductor devices | Kuo-Chiang Tsai | 2021-03-16 |
| 10950729 | Contact structure with insulating cap | Kuo-Chiang Tsai, Fu-Hsiang Su, Yi-Ju Chen | 2021-03-16 |
| 10879400 | Field effect transistor and method of manufacturing the same | Kuo-Chiang Tsai, Fu-Hsiang Su | 2020-12-29 |