Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141358 | Semiconductor switching device separated by device isolation | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen +1 more | 2018-11-27 |
| 10074612 | Method for forming alignment marks and structure of same | Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai +7 more | 2018-09-11 |
| 10062720 | Deep trench isolation fabrication for BSI image sensor | Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Chih-Hui Huang, Shyh-Fann Ting +2 more | 2018-08-28 |
| 9954022 | Extra doped region for back-side deep trench isolation | Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Jhy-Jyi Sze, Shyh-Fann Ting +4 more | 2018-04-24 |
| 9887234 | CMOS image sensor and method for forming the same | Min-Feng Kao, Wei-Cheng Hsu, Tzu-Jui Wang, Tzu-Hsuan Hsu, Jen-Cheng Liu +2 more | 2018-02-06 |
| 9754993 | Deep trench isolations and methods of forming the same | Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Min-Ying Tsai | 2017-09-05 |
| 9728570 | Deep trench isolation fabrication for BSI image sensor | Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Chih-Hui Huang, Shyh-Fann Ting +2 more | 2017-08-08 |
| 9704910 | Semiconductor switching device separated by device isolation | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen +1 more | 2017-07-11 |
| 9627326 | Method for forming alignment marks and structure of same | Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai +7 more | 2017-04-18 |
| 9570497 | Back side illuminated image sensor having isolated bonding pads | Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang | 2017-02-14 |
| 9559244 | CMOS image sensors and methods for forming the same | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Tzu-Hsuan Hsu | 2017-01-31 |
| 9536810 | Flat pad structure for integrating complementary metal-oxide-semiconductor (CMOS) image sensor processes | Yen-Ting Chiang, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Ming-Tsong Wang +2 more | 2017-01-03 |
| 9355964 | Method for forming alignment marks and structure of same | Cheng-Hsien Chou, Sheng-Chau Chen, Chun-Wei Chang, Kai-Chun Hsu, Chih-Yu Lai +7 more | 2016-05-31 |
| 9293502 | Semiconductor switching device separated by device isolation | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen +1 more | 2016-03-22 |
| 9281334 | Pickup device structure within a device isolation region | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen +1 more | 2016-03-08 |
| 9165970 | Back side illuminated image sensor having isolated bonding pads | Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang | 2015-10-20 |
| 9076708 | CMOS image sensors and methods for forming the same | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Tzu-Hsuan Hsu | 2015-07-07 |
| 9048162 | CMOS image sensors and methods for forming the same | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Tzu-Hsuan Hsu | 2015-06-02 |
| 8878242 | Pickup device structure within a device isolation region | Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen +1 more | 2014-11-04 |
| 8685820 | Multiple gate dielectric structures and methods of forming the same | Dun-Nian Yaung, Jen-Cheng Liu, Wen-I Hsu, Min-Feng Kao | 2014-04-01 |
| 8513587 | Image sensor with anti-reflection layer and method of manufacturing the same | Tzu-Jui Wang, Wei-Cheng Hsu, Dun-Nian Yaung, Jen-Cheng Liu | 2013-08-20 |
| 6833578 | Method and structure improving isolation between memory cell passing gate and capacitor | Kuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu, Chung-Wei Chang, Tien-Lu Lin +3 more | 2004-12-21 |
| 6656786 | MIM process for logic-based embedded RAM having front end manufacturing operation | Min-Hsiung Chiang, Hsien-Yuan Chang, Tazy-Schiuan Yang | 2003-12-02 |
| 6656785 | MIM process for logic-based embedded RAM | Min-Hsiung Chiang, Hsien-Yuan Chang | 2003-12-02 |
| 6436762 | Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins | Kuo-Chyuan Tzeng, Tse-Liang Ying, Min-Hsiung Chiang, Chung-Wei Chang | 2002-08-20 |