Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7545022 | Capacitor pairs with improved mismatch performance | Chia-Yi Chen, Chih-Ping Chao | 2009-06-09 |
| 7338909 | Micro-etching method to replicate alignment marks for semiconductor wafer photolithography | Yu-Liang Lin, Henry Lo, Gorge Huang, Tony Lu, Gnesh Yeh +8 more | 2008-03-04 |
| 7335956 | Capacitor device with vertically arranged capacitor regions of various kinds | Yueh-You Chen, Chih-Ping Chao, Chun-Hong Chen | 2008-02-26 |
| 7125521 | Method to solve alignment mark blinded issues and technology for application of semiconductor etching at a tiny area | Jui-Cheng Lo, Shang-Ting Tsai, Yu-Liang Lin | 2006-10-24 |
| 7061056 | High fMAX deep submicron MOSFET | Chao-Chieh Tsai, Shyh-Chyi Wong | 2006-06-13 |
| 7050290 | Integrated capacitor | Denny Tang, Wen-Chin Lin, Li-Shyue Lai, Chun-Hon Chen | 2006-05-23 |
| 7035083 | Interdigitated capacitor and method for fabrication thereof | Wen-Chin Lin, Denny Tang, Li-Shyue Lai, Chun-Hon Chen | 2006-04-25 |
| 6949781 | Metal-over-metal devices and the method for manufacturing same | Chun-Hon Chen | 2005-09-27 |
| 6888063 | Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling | Wai-Yi Lien, Jyh-Chyurn Guo, John Chern | 2005-05-03 |
| 6746966 | Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area | Henry Lo, Shang-Ting Tsai, Yu-Liang Lin | 2004-06-08 |
| 6737310 | Self-aligned process for a stacked gate RF MOSFET device | Chaochieh Tsai, Jui-Yu Chang, Shyh-Chyi Wong | 2004-05-18 |
| 6613623 | High fMAX deep submicron MOSFET | Chao-Chieh Tsai, Shyh-Chyi Wong | 2003-09-02 |
| 6559040 | Process for polishing the top surface of a polysilicon gate | Chen-Hua Yu, Syun-Ming Jang | 2003-05-06 |
| 6524906 | Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer | Syun-Ming Jang | 2003-02-25 |
| 6465294 | Self-aligned process for a stacked gate RF MOSFET device | Chaochieh Tsai, Ju-Yu Chang, Shyh-Chyi Wong | 2002-10-15 |
| 6444371 | Prevention of die loss to chemical mechanical polishing | Syun-Ming Jang, Jui-Yu Chang, Chen-Hua Yu, Tsu Shih, Jeng-Horng Chen | 2002-09-03 |
| 6410424 | Process flow to optimize profile of ultra small size photo resist free contact | Ming-Huan Tsai, Chii-Ming Wu, Hun-Jan Tao | 2002-06-25 |
| 6391792 | Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer | Syun-Ming Jang, Juing-Yi Cheng | 2002-05-21 |
| 6350693 | Method of CMP of polysilicon | Syun-Ming Jang | 2002-02-26 |
| 6271123 | Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG | Syun-Ming Jang | 2001-08-07 |
| 6268281 | Method to form self-aligned contacts with polysilicon plugs | Cheng-Yeh Shih, Jin-Yuan Lee | 2001-07-31 |
| 6242356 | Etchback method for forming microelectronic layer with enhanced surface smoothness | Syun-Ming Jang, Shwangming Jeng, Chen-Hua Yu | 2001-06-05 |
| 6207483 | Method for smoothing polysilicon gate structures in CMOS devices | Chu-Yun Fu, Syun-Ming Jang, Shwangming Jeng | 2001-03-27 |
| 6200875 | Chemical mechanical polishing of polysilicon plug using a silicon nitride stop layer | Syun-Ming Jang | 2001-03-13 |
| 6191039 | Method of CMP of polysilicon | Syun-Ming Jang | 2001-02-20 |