Issued Patents All Time
Showing 151–175 of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9640428 | Self-aligned repairing process for barrier layer | Chih-Chien Chi, Chung-Chi Ko, Mei-Ling Chen, Huang-Yi Huang, Szu-Ping Tung | 2017-05-02 |
| 9614052 | Copper contact plugs with barrier layers | Li-Lin Su, Huang-Ming Chen, Hsueh Wen Tsau | 2017-04-04 |
| 9589800 | Method for integrated circuit patterning | Szu-Ping Tung, Huang-Yi Huang, Neng-Jye Yang | 2017-03-07 |
| 9576892 | Semiconductor devices and methods of forming same | Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung | 2017-02-21 |
| 9567668 | Plasma apparatus, magnetic-field controlling method, and semiconductor manufacturing method | Chih-Chien Chi, Shing-Chyang Pan, Kuan-Chia Chen, Yao-Jen Chang, Huang-Yi Huang | 2017-02-14 |
| 9543198 | Structure and method for forming interconnect structure | Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung | 2017-01-10 |
| 9514928 | Selective repairing process for barrier layer | Chih-Chien Chi, Chung-Chi Ko, Mei-Ling Chen, Huang-Yi Huang, Szu-Ping Tung | 2016-12-06 |
| 9487864 | Metal capping process and processing platform thereof | Chih-Chien Chi, Szu-Ping Tung, Huang-Yi Huang | 2016-11-08 |
| 9472449 | Semiconductor structure with inlaid capping layer and method of manufacturing the same | Kuan-Chia Chen, Shing-Chyang Pan, Chih-Chien Chi | 2016-10-18 |
| 9385086 | Bi-layer hard mask for robust metallization profile | Shing-Chyang Pan, Hong-Hui Hsu | 2016-07-05 |
| 9330915 | Surface pre-treatment for hard mask fabrication | Shing-Chyang Pan, Hong-Hui Hsu, Yao-Jen Chang | 2016-05-03 |
| 9324606 | Self-aligned repairing process for barrier layer | Chih-Chien Chi, Chung-Chi Ko, Mei-Ling Chen, Huang-Yi Huang, Szu-Ping Tung | 2016-04-26 |
| 9275894 | Method for forming semiconductor device structure | Chi-Feng Lin, Kuan-Chia Chen | 2016-03-01 |
| 9218986 | Hard mask edge cover scheme | Szu-Ping Tung, Huang-Yi Huang, Chih-Chien Chi | 2015-12-22 |
| 9184134 | Method of manufacturing a semiconductor device structure | Chi-Feng Lin, Chih-Chien Chi | 2015-11-10 |
| 9136206 | Copper contact plugs with barrier layers | Li-Lin Su, Huang-Ming Chen, Hsueh Wen Tsau | 2015-09-15 |
| 9129814 | Method for integrated circuit patterning | Szu-Ping Tung, Huang-Yi Huang, Neng-Jye Yang | 2015-09-08 |
| 8980745 | Interconnect structures and methods of forming same | Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Minghsing Tsai | 2015-03-17 |
| 8940635 | Structure and method for forming interconnect structure | Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung | 2015-01-27 |
| 8629058 | Methods for via structure with improved reliability | Shau-Lin Shue, Cheng-Lin Huang | 2014-01-14 |
| 8627243 | Methods for optimizing conductor patterns for ECP and CMP in semiconductor processing | Chi-Feng Lin, Yu-Wei Chou, Wen-Cheng Huang, Cheng-I Huang | 2014-01-07 |
| 8361900 | Barrier layer for copper interconnect | Shing-Chyang Pan, Han-Hsin Kuo, Chung-Chi Ko | 2013-01-29 |
| 8264086 | Via structure with improved reliability | Shau-Lin Shue, Cheng-Lin Huang | 2012-09-11 |
| 8252690 | In situ Cu seed layer formation for improving sidewall coverage | Li-Lin Su, Cheng-Lin Huang, Shing-Chyang Pan | 2012-08-28 |
| 8236579 | Methods and systems for lithography alignment | Hsiao-Tzu Lu, Hung-Chang Hsieh, Kuei-Shun Chen, Hsueh-Hung Fu, Shau-Lin Shue | 2012-08-07 |