Issued Patents All Time
Showing 1–25 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12389674 | Low resistance fill metal layer material as stressor in metal gates | Mrunal A. Khaderbad, Ziwei Fang, Keng-Chu Lin | 2025-08-12 |
| 12046657 | Method of manufacturing a semiconductor device including capping layer, barrier layer and work function layer | — | 2024-07-23 |
| 12040364 | Semiconductor device structure | Chun-I Wu, Ziwei Fang, Huang-Lin Chao, I-Ming Chang, Chung-Liang Cheng +1 more | 2024-07-16 |
| 12033893 | Contact plug with impurity variation | Chung-Chiang Wu, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su | 2024-07-09 |
| 11935957 | Geometry for threshold voltage tuning on semiconductor device | Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Cheng-Yen Tsai +3 more | 2024-03-19 |
| 11923367 | Low resistance fill metal layer material as stressor in metal gates | Mrunal A. Khaderbad, Ziwei Fang, Keng-Chu Lin | 2024-03-05 |
| 11855181 | Tuning threshold voltage in field-effect transistors | Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung | 2023-12-26 |
| 11769694 | Contact plug with impurity variation | Chung-Chiang Wu, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su | 2023-09-26 |
| 11626493 | Semiconductor device structure | Chun-I Wu, Ziwei Fang, Huang-Lin Chao, I-Ming Chang, Chung-Liang Cheng +1 more | 2023-04-11 |
| 11404312 | Contact plug with impurity variation | Chung-Chiang Wu, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su | 2022-08-02 |
| 11404416 | Low resistance fill metal layer material as stressor in metal gates | Mrunal A. Khaderbad, Ziwei Fang, Keng-Chu Lin | 2022-08-02 |
| 11257923 | Tuning threshold voltage in field-effect transistors | Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung | 2022-02-22 |
| 11251131 | Copper contact plugs with barrier layers | Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen | 2022-02-15 |
| 11211465 | Semiconductor device having gate dielectric and inhibitor film over gate dielectric | Mrunal A. Khaderbad, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung +2 more | 2021-12-28 |
| 11127836 | Metal gate scheme for device and methods of forming | Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee | 2021-09-21 |
| 11094828 | Geometry for threshold voltage tuning on semiconductor device | Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Cheng-Yen Tsai +3 more | 2021-08-17 |
| 11038029 | Semiconductor device structure and method for forming the same | Chun-I Wu, Ziwei Fang, Huang-Lin Chao, I-Ming Chang, Chung-Liang Cheng +1 more | 2021-06-15 |
| 10985265 | Method for forming semiconductor device structure | Chung-Liang Cheng, I-Ming Chang, Hsiang-Pi Chang, Ziwei Fang, Huang-Lin Chao | 2021-04-20 |
| 10978357 | Semiconductor arrangement and method of manufacture | I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Ziwei Fang | 2021-04-13 |
| 10867848 | Semiconductor device and method | Chung-Chiang Wu, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su | 2020-12-15 |
| 10818767 | Semiconductor device having a metal gate electrode stack | — | 2020-10-27 |
| 10741400 | Gate replacement structures in semiconductor devices | Chia-Ching Lee, Chung-Chiang Wu, Da-Yuan Lee | 2020-08-11 |
| 10700010 | Copper contact plugs with barrier layers | Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen | 2020-06-30 |
| 10692770 | Geometry for threshold voltage tuning on semiconductor device | Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Cheng-Yen Tsai +3 more | 2020-06-23 |
| 10510854 | Semiconductor device having gate body and inhibitor film between conductive prelayer over gate body and conductive layer over inhibitor film | Mrunal A. Khaderbad, Chia-Ching Lee, Da-Yuan Lee, Hsiao-Kuan Wei, Chih-Chang Hung +2 more | 2019-12-17 |