Issued Patents All Time
Showing 51–75 of 262 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11387114 | Semiconductor device with dummy gate and metal gate and method of fabricating the same | Wei-Cheng Wu, Harry-Hak-Lay Chuang | 2022-07-12 |
| 11335786 | Gate structure in high-κ metal gate technology | Wei-Cheng Wu, Shih-Hao Lo, Hung-Pin Ko | 2022-05-17 |
| 11302691 | High voltage integration for HKMG technology | Kong-Beng Thei, Chien-Chih Chou, Fu-Jier Fan, Hsiao-Chin Tuan, Yi-Huan Chen +1 more | 2022-04-12 |
| 11276684 | Recessed composite capacitor | Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei | 2022-03-15 |
| 11251314 | Memory devices and methods of manufacture thereof | Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu | 2022-02-15 |
| 11251286 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen | 2022-02-15 |
| 11244857 | Semiconductor structure and manufacturing method thereof | Yung-Chih Tsai, Wei-Che Hsu, Yu Yang | 2022-02-08 |
| 11189613 | Semiconductor device | Jia-Rui Lee, Kuo-Ming Wu, Yi-Chun Lin | 2021-11-30 |
| 11189628 | Trench gate high voltage transistor for embedded memory | Wei-Cheng Wu, Chien-Hung Chang | 2021-11-30 |
| 11171015 | Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer | Yu-Hung Cheng, Cheng-Ta Wu, Chen-Hao Chiang, Yeur-Luen Tu, Eugene Chen | 2021-11-09 |
| 11139367 | High density MIM capacitor structure | Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Jung-I Lin, Jhy-Jyi Sze +3 more | 2021-10-05 |
| 11133226 | FUSI gated device formation | Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Kong-Beng Thei +1 more | 2021-09-28 |
| 11121038 | Spacer structure and manufacturing method thereof | Kong-Beng Thei | 2021-09-14 |
| 11069652 | Method of manufacturing semiconductor structure | Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh +9 more | 2021-07-20 |
| 11063157 | Trench capacitor profile to decrease substrate warpage | Hsin-Li Cheng, Jyun-Ying Lin, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu +4 more | 2021-07-13 |
| 11063081 | Device over photodetector pixel sensor | Jhy-Jyi Sze, Dun-Nian Yaung | 2021-07-13 |
| 11063080 | Implant damage free image sensor and method of the same | Jhy-Jyi Sze, Dun-Nian Yaung, Chen-Jong Wang, Yimin Huang, Yuichiro Yamashita | 2021-07-13 |
| 11063038 | Through silicon via design for stacking integrated circuits | Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan +2 more | 2021-07-13 |
| 11049797 | Method for manufacturing a semiconductor structure comprising a semiconductor device layer formed on a tem, porary substrate having a graded SiGe etch stop layer therebetween | Yu-Hung Cheng, Shih Pei Chou, Yeur-Luen Tu, Tung-I Lin, Wei-Li Chen | 2021-06-29 |
| 11043531 | Semiconductor structure and manufacturing method of the same | Sheng-Huang Huang, Harry-Hak-Lay Chuang, Jiunyu Tsai, Hung Cho Wang | 2021-06-22 |
| 11037982 | Semiconductor structure integrated with magnetic tunneling junction | Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang | 2021-06-15 |
| 11029714 | Flipped gate current reference and method of using | Mohammad Al-Shyoukh | 2021-06-08 |
| 11011619 | Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices | Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen | 2021-05-18 |
| 10964692 | Through silicon via design for stacking integrated circuits | Kong-Beng Thei, Dun-Nian Yaung, Fu-Jier Fan, Hsing-Chih Lin, Hsiao-Chin Tuan +2 more | 2021-03-30 |
| 10879200 | Sidewall spacer to reduce bond pad necking and/or redistribution layer necking | Kong-Beng Thei | 2020-12-29 |