Issued Patents All Time
Showing 51–75 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10217762 | Doping channels of edge cells to provide uniform programming speed and reduce read disturb | Xuehong Yu | 2019-02-26 |
| 10210941 | Reducing injection type of read disturb in a cold read of a memory device | Hong-Yan Chen | 2019-02-19 |
| 10204689 | Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate | Ching-Huang Lu, Anubhav Khandelwal, Changyuan Chen, Cynthia Hsu | 2019-02-12 |
| 10157676 | Dynamic tuning of first read countermeasures | Liang Pang, Jiahui Yuan, Charles See Yeung Kwong | 2018-12-18 |
| 10153051 | Program-verify of select gate transistor with doped channel in NAND string | Hong-Yan Chen, Yen-Lung Li | 2018-12-11 |
| 10134479 | Non-volatile memory with reduced program speed variation | Zhengyi Zhang | 2018-11-20 |
| 10128257 | Select transistors with tight threshold voltage in 3D memory | Liang Pang, Jayavel Pachamuthu | 2018-11-13 |
| 10121552 | Reducing charge loss in data memory cell adjacent to dummy memory cell | Ashish Baraskar, Liang Pang, Ching-Huang Lu, Nan Lu, Hong-Yan Chen | 2018-11-06 |
| 10115464 | Electric field to reduce select gate threshold voltage shift | Ching-Huang Lu | 2018-10-30 |
| 10068657 | Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels | Xuehong Yu, Liang Pang | 2018-09-04 |
| 10068651 | Channel pre-charge to suppress disturb of select gate transistors during erase in memory | Vinh Diep, Wei Zhao, Ashish Baraskar, Ching-Huang Lu | 2018-09-04 |
| 10038005 | Sense circuit having bit line clamp transistors with different threshold voltages for selectively boosting current in NAND strings | Zhengyi Zhang, Henry Chin | 2018-07-31 |
| 10026487 | Non-volatile memory with customized control of injection type of disturb during program verify for improved program performance | Hong-Yan Chen | 2018-07-17 |
| 10020314 | Forming memory cell film in stack opening | Ashish Baraskar, Liang Pang, Yanli Zhang, Ching-Huang Lu | 2018-07-10 |
| 10008277 | Block health monitoring using threshold voltage of dummy memory cells | Liang Pang, Xuehong Yu, Nian Niles Yang | 2018-06-26 |
| 10008271 | Programming of dummy memory cell to reduce charge loss in select gate transistor | Vinh Diep, Ching-Huang Lu | 2018-06-26 |
| 9984760 | Suppressing disturb of select gate transistors during erase in memory | Zhengyi Zhang, Liang Pang | 2018-05-29 |
| 9959932 | Grouping memory cells into sub-blocks for program speed uniformity | Zhengyi Zhang, James Kai, Johann Alsmeier | 2018-05-01 |
| 9947407 | Techniques for programming of select gates in NAND memory | Hao Thai Nguyen, Man Lung Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki | 2018-04-17 |
| 9941293 | Select transistors with tight threshold voltage in 3D memory | Liang Pang, Jayavel Pachamuthu | 2018-04-10 |
| 9922992 | Doping channels of edge cells to provide uniform programming speed and reduce read disturb | Xuehong Yu | 2018-03-20 |
| 9922714 | Temperature dependent erase in non-volatile storage | Xuehong Yu | 2018-03-20 |
| 9922705 | Reducing select gate injection disturb at the beginning of an erase operation | Vinh Diep, Xuehong Yu, Zhengyi Zhang | 2018-03-20 |
| 9911500 | Dummy voltage to reduce first read effect in memory | Liang Pang, Pao-Ling Koh, Jiahui Yuan, Charles See Yeung Kwong | 2018-03-06 |
| 9905305 | Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines | Hong-Yan Chen | 2018-02-27 |