Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11101228 | Integrated circuit package with a magnetic core | Jonghae Kim, Milind Shah | 2021-08-24 |
| 10861852 | Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits | Xia Li, Shashank S. Ekbote | 2020-12-08 |
| 10840884 | Bulk acoustic wave (BAW) and passive-on-glass (POG) filter co-integration | Stanley Seungchul Song, Jonghae Kim | 2020-11-17 |
| 10825536 | Programmable circuits for performing machine learning operations on edge devices | Haining Yang | 2020-11-03 |
| 10756206 | High power compound semiconductor field effect transistor devices with low doped drain | Bin Yang, Xia Li, Gengming Tao | 2020-08-25 |
| 10651122 | Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS) | Junjing Bao, Giridhar Nallapati | 2020-05-12 |
| 10461164 | Compound semiconductor field effect transistor with self-aligned gate | Bin Yang, Xia Li, Gengming Tao | 2019-10-29 |
| 10418244 | Modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area | Stanley Seungchul Song, Giridhar Nallapati | 2019-09-17 |
| 10291211 | Adaptive pulse generation circuits for clocking pulse latches with minimum hold time | Stanley Seungchul Song, Seong-Ook Jung, Hanwool Jeong, Tae Woo Oh, Giridhar Nallapati | 2019-05-14 |
| 10247617 | Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) | Lixin Ge, Bin Yang, Jiefeng Lin, Giridhar Nallapati, Bo Yu +3 more | 2019-04-02 |
| 10164054 | Compound semiconductor field effect transistor with self-aligned gate | Bin Yang, Gengming Tao, Xia Li | 2018-12-25 |
| 10141305 | Semiconductor devices employing field effect transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts | Jeffrey Junhao Xu, Haining Yang, Jun Yuan, Kern Rim | 2018-11-27 |
| 10090244 | Standard cell circuits employing high aspect ratio voltage rails for reduced resistance | Jeffrey Junhao Xu, Mustafa Badaroglu, Da Yang | 2018-10-02 |
| 10084074 | Compound semiconductor field effect transistor gate length scaling | Bin Yang, Gengming Tao, Xia Li | 2018-09-25 |
| 9997617 | Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods | Bin Yang, Xia Li | 2018-06-12 |
| 9048180 | Low stress sacrificial cap layer | Jiong-Ping Lu, Srinivasan Chakravarthi | 2015-06-02 |
| 8846487 | Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology | Angelo Pinto, Rick L. Wise | 2014-09-30 |
| 7994073 | Low stress sacrificial cap layer | Jiong-Ping Lu, Srinivasan Chakravarthi | 2011-08-09 |
| 7786518 | Growth of unfaceted SiGe in MOS transistor fabrication | Srinivasan Chakravarthi | 2010-08-31 |
| 7700467 | Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige | Haowen Bu, Scott Bushman | 2010-04-20 |
| 7642197 | Method to improve performance of secondary active components in an esige CMOS technology | Angelo Pinto | 2010-01-05 |
| 7569499 | Semiconductor device made by multiple anneal of stress inducing layer | — | 2009-08-04 |
| 7553717 | Recess etch for epitaxial SiGe | Srinivasan Chakravarthi, Johan W. Weijtmans | 2009-06-30 |
| 7553718 | Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps | Haowen Bu, Rajesh Khamankar, Douglas T. Grider | 2009-06-30 |
| 7348232 | Highly activated carbon selective epitaxial process for CMOS | Srinivasan Charkravarthi | 2008-03-25 |