Issued Patents All Time
Showing 376–400 of 448 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5585282 | Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor | Alan G. Wood, Warren M. Farnworth, Tim J. Corbett | 1996-12-17 |
| 5540810 | IC mechanical planarization process incorporating two slurry compositions for faster material removal times | Gurtej S. Sandhu, Richard L. Elliott, Jody D. Larsen | 1996-07-30 |
| 5536606 | Method for making self-aligned rim phase shifting masks for sub-micron lithography | — | 1996-07-16 |
| 5514245 | Method for chemical planarization (CMP) of a semiconductor wafer to provide a planar surface free of microscratches | Malcolm Grief, Laurence D. Schultz | 1996-05-07 |
| 5496762 | Highly resistive structures for integrated circuits and method of manufacturing the same | Gurtej S. Sandhu, David A. Cathey | 1996-03-05 |
| 5486129 | System and method for real-time control of semiconductor a wafer polishing, and a polishing head | Gurtej S. Sandhu | 1996-01-23 |
| 5439551 | Chemical-mechanical polishing techniques and methods of end point detection in chemical-mechanical polishing processes | Scott Meikle | 1995-08-08 |
| 5438240 | Field emission structures produced on macro-grain polysilicon substrates | David A. Cathey, J. Brett Rolfson, Tyler Lowrey | 1995-08-01 |
| 5421769 | Apparatus for planarizing semiconductor wafers, and a polishing pad for a planarization apparatus | Laurence D. Schultz, Mark E. Tuttle | 1995-06-06 |
| 5416048 | Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage | Guy T. Blalock | 1995-05-16 |
| 5397908 | Arrays of memory integrated circuitry | Charles H. Dennison | 1995-03-14 |
| 5395801 | Chemical-mechanical polishing processes of planarizing insulating layers | Scott Meikle | 1995-03-07 |
| 5391511 | Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor | Charles H. Dennison | 1995-02-21 |
| 5384284 | Method to form a low resistant bond pad interconnect | Mark E. Tuttle | 1995-01-24 |
| 5380678 | Bilayer barrier metal method for obtaining 100% step-coverage in contact vias without junction degradation | Chang Yu | 1995-01-10 |
| 5376405 | Chemical vapor deposition technique for depositing titanium silicide on semiconductor wafers | Gurtej S. Sandhu | 1994-12-27 |
| 5372974 | Approach to avoid buckling in BPSG by using an intermediate barrier layer | Randhir P. S. Thakur, Yauh-Ching Liu | 1994-12-13 |
| 5372973 | Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology | J. Brett Rolfson, Tyler Lowrey, David A. Cathey | 1994-12-13 |
| 5354490 | Slurries for chemical mechanically polishing copper containing metal layers | Chris C. Yu | 1994-10-11 |
| 5346585 | Use of a faceted etch process to eliminate stringers | Guy T. Blalock | 1994-09-13 |
| 5346587 | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation | Charles H. Dennison | 1994-09-13 |
| 5344792 | Pulsed plasma enhanced CVD of metal silicide conductive films such as TiSi.sub.2 | Gurtej S. Sandhu | 1994-09-06 |
| 5329207 | Field emission structures produced on macro-grain polysilicon substrates | David A. Cathey, J. Brett Rolfson, Tyler Lowrey | 1994-07-12 |
| 5320880 | Method of providing a silicon film having a roughened outer surface | Gurtej S. Sandhu | 1994-06-14 |
| 5318927 | Methods of chemical-mechanical polishing insulating inorganic metal oxide materials | Gurtej S. Sandhu, Donald L. Westmoreland | 1994-06-07 |