Issued Patents All Time
Showing 1–25 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7485961 | Approach to avoid buckling in BPSG by using an intermediate barrier layer | Trung T. Doan, Randhir P. S. Thakur | 2009-02-03 |
| 6924522 | EEPROM transistor for a DRAM | Manny K. F. Ma | 2005-08-02 |
| 6806551 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material | Ruggero Castagnetti, Ramnath Venkatraman | 2004-10-19 |
| 6794698 | Formation of novel DRAM cell capacitors by integration of capacitors with isolation trench sidewalls | Dung-Ching Perng | 2004-09-21 |
| 6770947 | Laser-breakable fuse link with alignment and break point promotion structures | Gary K. Giust, Ruggero Castagnetti, Shiva Ramesh | 2004-08-03 |
| 6690044 | Approach to avoid buckling BPSG by using an intermediate barrier layer | Trung T. Doan, Randhir P. S. Thakur | 2004-02-10 |
| 6627968 | Integrated capacitor and fuse | Chuan-Cheng Cheng | 2003-09-30 |
| 6566730 | Laser-breakable fuse link with alignment and break point promotion structures | Gary K. Giust, Ruggero Castagnetti, Shiva Ramesh | 2003-05-20 |
| 6566171 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material | Ruggero Castagnetti, Ramnath Venkatraman | 2003-05-20 |
| 6495426 | Method for simultaneous formation of integrated capacitor and fuse | Chuan-Cheng Cheng | 2002-12-17 |
| 6472715 | Reduced soft error rate (SER) construction for integrated circuit structures | Helmut Puchner, Ruggero Castagnetti, Weiran Kong, Lee Phan, Franklin Duan +1 more | 2002-10-29 |
| 6442061 | Single channel four transistor SRAM | Weiran Kong, Gary K. Giust, Ramnath Venkatraman, Franklin Duan, Ruggero Castagnetti +3 more | 2002-08-27 |
| 6413848 | Self-aligned fuse structure and method with dual-thickness dielectric | Gary K. Giust, Ruggero Castagnetti, Subramanian Ramesh | 2002-07-02 |
| 6391755 | Method of making EEPROM transistor for a DRAM | Manny K. F. Ma | 2002-05-21 |
| 6369418 | Formation of a novel DRAM cell | Dung-Ching Perng | 2002-04-09 |
| 6365452 | DRAM cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation | Dung-Ching Perng | 2002-04-02 |
| 6316312 | Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures | David Y. Kao | 2001-11-13 |
| 6259146 | Self-aligned fuse structure and method with heat sink | Gary K. Giust, Ruggero Castagnetti, Subramanian Ramesh | 2001-07-10 |
| 6218276 | Silicide encapsulation of polysilicon gate and interconnect | Gary K. Giust, Ruggero Castagnetti, Subramanian Ramesh | 2001-04-17 |
| 6177699 | DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation | Dung-Ching Perng | 2001-01-23 |
| 6177328 | Methods of forming capacitors methods of forming DRAM cells, and integrated circuits incorporating structures and DRAM cell structures | David Y. Kao | 2001-01-23 |
| 6175129 | Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures | David Y. Kao | 2001-01-16 |
| 6166403 | Integrated circuit having embedded memory with electromagnetic shield | Ruggero Castagnetti, Subramanian Ramesh | 2000-12-26 |
| 6162714 | Method of forming thin polygates for sub quarter micron CMOS process | Ruggero Castagnetti, Gary K. Giust, Subramanian Ramesh | 2000-12-19 |
| 6090239 | Method of single step damascene process for deposition and global planarization | Dung-Ching Perng | 2000-07-18 |