Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8738940 | Power controller for SoC power gating applications | Ramnath Venkatraman, Shashidhara S. Bapat | 2014-05-27 |
| 8589853 | Total power optimization for a logic integrated circuit | Benjamin Mbouombouo, Ramnath Venkatraman | 2013-11-19 |
| 8411399 | Defectivity-immune technique of implementing MIM-based decoupling capacitors | Ramnath Venkatraman | 2013-04-02 |
| 8112734 | Optimization with adaptive body biasing | Benjamin Mbouombouo, Ramnath Venkatraman | 2012-02-07 |
| 7869251 | SRAM based one-time-programmable memory | Ramnath Venkatraman, Subramanian Ramesh | 2011-01-11 |
| 7440356 | Modular design of multiport memory bitcells | Ramnath Venkatraman, Subramanian Ramesh | 2008-10-21 |
| 7304874 | Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas | Ramnath Venkatraman, Joseph Eugene Glenn | 2007-12-04 |
| 7082067 | Circuit for verifying the write speed of SRAM cells | Ramnath Venkatraman | 2006-07-25 |
| 7042747 | Ternary CAM bitcells | Ramnath Venkatraman, Joseph Eugene Glenn | 2006-05-09 |
| 7006370 | Memory cell architecture | Subramanian Ramesh, Ramnath Venkatraman | 2006-02-28 |
| 6980462 | Memory cell architecture for reduced routing congestion | Subramanian Ramesh, Ramnath Venkatraman | 2005-12-27 |
| 6977512 | Method and apparatus for characterizing shared contacts in high-density SRAM cell design | Franklin Duan, Subramanian Ramesh | 2005-12-20 |
| 6978407 | Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory | Franklin Duan, Subramanian Ramesh | 2005-12-20 |
| 6934174 | Reconfigurable memory arrays | Ramnath Venkatraman, Subramanian Ramesh | 2005-08-23 |
| 6828653 | Method of forming metal fuses in CMOS processes with copper interconnect | Prabhakar P. Tripathi, Ramnath Venkatraman | 2004-12-07 |
| 6806551 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material | Yauh-Ching Liu, Ramnath Venkatraman | 2004-10-19 |
| 6778462 | Metal-programmable single-port SRAM array for dual-port functionality | Ramnath Ventatraman, Subramanian Ramesh | 2004-08-17 |
| 6770947 | Laser-breakable fuse link with alignment and break point promotion structures | Gary K. Giust, Yauh-Ching Liu, Shiva Ramesh | 2004-08-03 |
| 6687114 | High density memory with storage capacitor | Arvind Kamath | 2004-02-03 |
| 6664141 | Method of forming metal fuses in CMOS processes with copper interconnect | Prabhakar P. Tripathi, Ramnath Venkatraman | 2003-12-16 |
| 6586291 | High density memory with storage capacitor | Arvind Kamath | 2003-07-01 |
| 6566730 | Laser-breakable fuse link with alignment and break point promotion structures | Gary K. Giust, Yauh-Ching Liu, Shiva Ramesh | 2003-05-20 |
| 6566171 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material | Yauh-Ching Liu, Ramnath Venkatraman | 2003-05-20 |
| 6472715 | Reduced soft error rate (SER) construction for integrated circuit structures | Yauh-Ching Liu, Helmut Puchner, Weiran Kong, Lee Phan, Franklin Duan +1 more | 2002-10-29 |
| 6442061 | Single channel four transistor SRAM | Weiran Kong, Gary K. Giust, Ramnath Venkatraman, Yauh-Ching Liu, Franklin Duan +3 more | 2002-08-27 |