Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9158319 | Closed-loop adaptive voltage scaling for integrated circuits | Manjunatha Gowda, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao | 2015-10-13 |
| 8738940 | Power controller for SoC power gating applications | Shashidhara S. Bapat, Ruggero Castagnetti | 2014-05-27 |
| 8624352 | Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank | Bonnie E. Weir, Edward B. Harris | 2014-01-07 |
| 8589853 | Total power optimization for a logic integrated circuit | Benjamin Mbouombouo, Ruggero Castagnetti | 2013-11-19 |
| 8429586 | Basic cell architecture for structured ASICs | Michael N. Dillon, David A. Gardner, Carl Monzel, Subramanian Ramesh, Robert C. Armstrong +2 more | 2013-04-23 |
| 8411399 | Defectivity-immune technique of implementing MIM-based decoupling capacitors | Ruggero Castagnetti | 2013-04-02 |
| 8178909 | Integrated circuit cell architecture configurable for memory or logic elements | Carl Monzel, Subramanian Ramesh | 2012-05-15 |
| 8166440 | Basic cell architecture for structured application-specific integrated circuits | Michael N. Dillon, David A. Gardner, Carl Monzel, Subramanian Ramesh, Robert C. Armstrong +2 more | 2012-04-24 |
| 8112734 | Optimization with adaptive body biasing | Benjamin Mbouombouo, Ruggero Castagnetti | 2012-02-07 |
| 8044437 | Integrated circuit cell architecture configurable for memory or logic elements | Carl Monzel, Subramanian Ramesh | 2011-10-25 |
| 7869251 | SRAM based one-time-programmable memory | Ruggero Castagnetti, Subramanian Ramesh | 2011-01-11 |
| 7440356 | Modular design of multiport memory bitcells | Ruggero Castagnetti, Subramanian Ramesh | 2008-10-21 |
| 7404154 | Basic cell architecture for structured application-specific integrated circuits | Michael N. Dillon, David A. Gardner, Carl Monzel, Subramanian Ramesh, Robert C. Armstrong +2 more | 2008-07-22 |
| 7304874 | Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas | Ruggero Castagnetti, Joseph Eugene Glenn | 2007-12-04 |
| 7082067 | Circuit for verifying the write speed of SRAM cells | Ruggero Castagnetti | 2006-07-25 |
| 7069535 | Optical proximity correction method using weighted priorities | Olga A. Kobozeva, Mario Garza | 2006-06-27 |
| 7042747 | Ternary CAM bitcells | Ruggero Castagnetti, Joseph Eugene Glenn | 2006-05-09 |
| 7006370 | Memory cell architecture | Subramanian Ramesh, Ruggero Castagnetti | 2006-02-28 |
| 7006369 | Design and use of a spacer cell to support reconfigurable memories | Rugger Castagnetti, Subramanian Ramesh | 2006-02-28 |
| 6980462 | Memory cell architecture for reduced routing congestion | Subramanian Ramesh, Ruggero Castagnetti | 2005-12-27 |
| 6934174 | Reconfigurable memory arrays | Ruggero Castagnetti, Subramanian Ramesh | 2005-08-23 |
| 6828653 | Method of forming metal fuses in CMOS processes with copper interconnect | Ruggero Castagnetti, Prabhakar P. Tripathi | 2004-12-07 |
| 6806551 | Fuse construction for integrated circuit structure having low dielectric constant dielectric material | Yauh-Ching Liu, Ruggero Castagnetti | 2004-10-19 |
| 6713381 | Method of forming semiconductor device including interconnect barrier layers | Alexander L. Barr, Suresh Venkatesan, David B. Clegg, Rebecca G. Cole, Olubunmi O. Adetutu +5 more | 2004-03-30 |
| 6664141 | Method of forming metal fuses in CMOS processes with copper interconnect | Ruggero Castagnetti, Prabhakar P. Tripathi | 2003-12-16 |