Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9753667 | High bandwidth memory and glitch-less differential XOR | Travis R. Hebig, Myron Buer, Richard J. Stephani | 2017-09-05 |
| 9324451 | All voltage, temperature and process monitor circuit for memories | Saket Gupta, Yifei Zhang, Mark Winter | 2016-04-26 |
| 8705268 | Quantifying the read and write margins of memory bit cells | Myron Buer, Yifei Zhang | 2014-04-22 |
| 8429586 | Basic cell architecture for structured ASICs | Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Subramanian Ramesh, Robert C. Armstrong +2 more | 2013-04-23 |
| 8178909 | Integrated circuit cell architecture configurable for memory or logic elements | Ramnath Venkatraman, Subramanian Ramesh | 2012-05-15 |
| 8166440 | Basic cell architecture for structured application-specific integrated circuits | Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Subramanian Ramesh, Robert C. Armstrong +2 more | 2012-04-24 |
| 8044437 | Integrated circuit cell architecture configurable for memory or logic elements | Ramnath Venkatraman, Subramanian Ramesh | 2011-10-25 |
| 7404154 | Basic cell architecture for structured application-specific integrated circuits | Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Subramanian Ramesh, Robert C. Armstrong +2 more | 2008-07-22 |
| 7190185 | Methodology to measure many more transistors on the same test area | Franklin Duan, Minxuan Liu, John Quillian Walker, II, Nabil Monsour | 2007-03-13 |
| 6982891 | Re-configurable content addressable/dual port memory | — | 2006-01-03 |
| 6879524 | Memory I/O buffer using shared read/write circuitry | — | 2005-04-12 |
| 6864716 | Reconfigurable memory architecture | Michael N. Dillon, Bret Alan Oeltjen | 2005-03-08 |
| 6734744 | SRAM process monitor cell | Brandon Bartz | 2004-05-11 |
| 6687183 | Compiled variable internal self time memory | Steven Michael Peterson, Sifang Wu, Mai T. MAC LENNAN | 2004-02-03 |
| 6667912 | Timing scheme for semiconductor memory devices | — | 2003-12-23 |
| 6542434 | Programmable self time circuitry for memories | — | 2003-04-01 |
| 6498758 | Twisted bitlines to reduce coupling effects (dual port memories) | Sudeep Ashok Pomar | 2002-12-24 |