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High bandwidth memory and glitch-less differential XOR |
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2017-09-05 |
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All voltage, temperature and process monitor circuit for memories |
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2016-04-26 |
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Quantifying the read and write margins of memory bit cells |
Myron Buer, Yifei Zhang |
2014-04-22 |
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Basic cell architecture for structured ASICs |
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2013-04-23 |
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Integrated circuit cell architecture configurable for memory or logic elements |
Ramnath Venkatraman, Subramanian Ramesh |
2012-05-15 |
| 8166440 |
Basic cell architecture for structured application-specific integrated circuits |
Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Subramanian Ramesh, Robert C. Armstrong +2 more |
2012-04-24 |
| 8044437 |
Integrated circuit cell architecture configurable for memory or logic elements |
Ramnath Venkatraman, Subramanian Ramesh |
2011-10-25 |
| 7404154 |
Basic cell architecture for structured application-specific integrated circuits |
Ramnath Venkatraman, Michael N. Dillon, David A. Gardner, Subramanian Ramesh, Robert C. Armstrong +2 more |
2008-07-22 |
| 7190185 |
Methodology to measure many more transistors on the same test area |
Franklin Duan, Minxuan Liu, John Quillian Walker, II, Nabil Monsour |
2007-03-13 |
| 6982891 |
Re-configurable content addressable/dual port memory |
— |
2006-01-03 |
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Memory I/O buffer using shared read/write circuitry |
— |
2005-04-12 |
| 6864716 |
Reconfigurable memory architecture |
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2005-03-08 |
| 6734744 |
SRAM process monitor cell |
Brandon Bartz |
2004-05-11 |
| 6687183 |
Compiled variable internal self time memory |
Steven Michael Peterson, Sifang Wu, Mai T. MAC LENNAN |
2004-02-03 |
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Timing scheme for semiconductor memory devices |
— |
2003-12-23 |
| 6542434 |
Programmable self time circuitry for memories |
— |
2003-04-01 |
| 6498758 |
Twisted bitlines to reduce coupling effects (dual port memories) |
Sudeep Ashok Pomar |
2002-12-24 |