Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9959926 | Method and apparatus for selective write assist using shared boost capacitor | Travis R. Hebig, Daniel Mark Nelson | 2018-05-01 |
| 9753667 | High bandwidth memory and glitch-less differential XOR | Travis R. Hebig, Myron Buer, Carl Monzel | 2017-09-05 |
| 8850109 | Content addressable memory data clustering block architecture | David B. Grover, Gordon W. Priebe | 2014-09-30 |
| 8787099 | Adjusting access times to memory cells based on characterized word-line delay and gate delay | Donald Albert Evans, Rasoju Veerabadra Chary, Bijan Kumar Ghosh, Christopher D. Sonnek | 2014-07-22 |
| 8773942 | Segmented memory having power-saving mode | Gordon W. Priebe, Ankur Goel | 2014-07-08 |
| 8773927 | Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay | Donald Albert Evans, Rasoju Veerabadra Chary, Bijan Kumar Ghosh, Ronald Brian Steele | 2014-07-08 |
| 8610461 | Split decode latch with shared feedback | Amy R. Rittenhouse, Donald Albert Evans | 2013-12-17 |
| 8462562 | Memory device with area efficient power gating circuitry | Ankur Goel, Donald Albert Evans, Dennis E. Dudeck, Ronald James Wozniak, Dharmendra Kumar Rai +2 more | 2013-06-11 |
| 8264862 | Low power SRAM based content addressable memory | Gordon W. Priebe | 2012-09-11 |
| 7603513 | ROM-based multiple match circuit | — | 2009-10-13 |
| 7325092 | Apparatus and methods for a static mux-based priority encoder | — | 2008-01-29 |
| 7117420 | Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories | Max M. Yeung, Miguel A. Vilchis | 2006-10-03 |