Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6413848 | Self-aligned fuse structure and method with dual-thickness dielectric | Gary K. Giust, Yauh-Ching Liu, Subramanian Ramesh | 2002-07-02 |
| 6259146 | Self-aligned fuse structure and method with heat sink | Gary K. Giust, Yauh-Ching Liu, Subramanian Ramesh | 2001-07-10 |
| 6218276 | Silicide encapsulation of polysilicon gate and interconnect | Yauh-Ching Liu, Gary K. Giust, Subramanian Ramesh | 2001-04-17 |
| 6166403 | Integrated circuit having embedded memory with electromagnetic shield | Yauh-Ching Liu, Subramanian Ramesh | 2000-12-26 |
| 6162714 | Method of forming thin polygates for sub quarter micron CMOS process | Yauh-Ching Liu, Gary K. Giust, Subramanian Ramesh | 2000-12-19 |
| 6144076 | Well formation For CMOS devices integrated circuit structures | Helmut Puchner, Shih-Fen Huang | 2000-11-07 |
| 6066525 | Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process | Yauh-Ching Liu, Subramanian Ramesh | 2000-05-23 |
| 6061264 | Self-aligned fuse structure and method with anti-reflective coating | Gary K. Giust, Yauh-Ching Liu, Subramanian Ramesh | 2000-05-09 |
| 6037233 | Metal-encapsulated polysilicon gate and interconnect | Yauh-Ching Liu, Gary K. Giust, Subramanian Ramesh | 2000-03-14 |
| 5953614 | Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step | Yauh-Ching Liu, Gary K. Giust, Subramanian Ramesh | 1999-09-14 |