Issued Patents All Time
Showing 51–65 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5139974 | Semiconductor manufacturing process for decreasing the optical refelctivity of a metal layer | Gurtej S. Sandhu, Chang Yu | 1992-08-18 |
| 5122476 | Double DRAM cell | Pierre C. Fazan, Hiang C. Chan, Gurtej S. Sandhu, Howard E. Rhodes | 1992-06-16 |
| 5108943 | Mushroom double stacked capacitor | Gurtej S. Sandhu, Pierre C. Fazan, Hiang C. Chan | 1992-04-28 |
| 5100825 | Method of making stacked surrounding reintrant wall capacitor | Pierre C. Fazan, Howard E. Rhodes, Charles H. Dennison | 1992-03-31 |
| 5089986 | Mushroom double stacked capacitor | Gurtej S. Sandhu, Pierre C. Fazan, Hiang C. Chan | 1992-02-18 |
| 5084406 | Method for forming low resistance DRAM digit-line | Howard E. Rhodes, Pierre C. Fazan, Hiang C. Chan, Charles H. Dennison | 1992-01-28 |
| 5084405 | Process to fabricate a double ring stacked cell structure | Pierre C. Fazan, Hiang C. Chan, Chuck Dennison, Howard E. Rhodes | 1992-01-28 |
| 5082797 | Method of making stacked textured container capacitor | Hiang C. Chan, Pierre C. Fazan | 1992-01-21 |
| 5081559 | Enclosed ferroelectric stacked capacitor | Pierre C. Fazan, Hiang C. Chan | 1992-01-14 |
| 5061650 | Method for formation of a stacked capacitor | Charles H. Dennison, Hiang C. Chan, Pierre C. Fazan, Howard E. Rhodes | 1991-10-29 |
| 5057888 | Double DRAM cell | Pierre C. Fazan, Hiang C. Chan, Gurtej S. Sandhu, Howard E. Rhodes | 1991-10-15 |
| 5053351 | Method of making stacked E-cell capacitor DRAM cell | Pierre C. Fazan, Hiang C. Chan, Howard E. Rhodes, Charles H. Dennison | 1991-10-01 |
| 5049517 | Method for formation of a stacked capacitor | Pierre C. Fazan, Hiang C. Chan, Howard E. Rhodes, Charles H. Dennison | 1991-09-17 |
| 5013680 | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Tyler Lowrey, Randal W. Chance, D. Mark Durcan, Ruojia Lee, Charles H. Dennison +3 more | 1991-05-07 |
| 4981810 | Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers | Pierre C. Fazan, Charles H. Dennison, Ruojia Lee | 1991-01-01 |