GB

Guy T. Blalock

Micron: 189 patents #49 of 6,345Top 1%
📍 Boise, ID: #20 of 3,546 inventorsTop 1%
🗺 Idaho: #31 of 8,810 inventorsTop 1%
Overall (All Time): #3,824 of 4,157,543Top 1%
189
Patents All Time

Issued Patents All Time

Showing 126–150 of 189 patents

Patent #TitleCo-InventorsDate
6274498 Methods of forming materials within openings, and method of forming isolation regions John T. Moore 2001-08-14
6274897 Semiconductor structure having interconnects on a projecting region and substrate Scott Meikle, Sung-Cheol Kim, Kirk D. Prall 2001-08-14
6251802 Methods of forming carbon-containing layers John T. Moore, Scott DeBoer 2001-06-26
6237483 Global planarization method and apparatus 2001-05-29
6232219 Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures Bradley J. Howard 2001-05-15
6228772 Method of removing surface defects or other recesses during the formation of a semiconductor device Bradley J. Howard, Mark E. Jost 2001-05-08
6222273 System having vias including conductive spacers Fernando Gonzalez 2001-04-24
6221205 Apparatus for improving the performance of a temperature-sensitive etch Bradley J. Howard 2001-04-24
6207571 Self-aligned contact formation for semiconductor devices Werner Juengling, Kirk D. Prall, Trung T. Doan, David Dickerson, David S. Becker 2001-03-27
6184146 Plasma producing tools, dual-source plasma etchers, dual-source plasma etching methods, and method of forming planar coil dual-source plasma etchers Kevin G. Donohoe 2001-02-06
6171964 Method of forming a conductive spacer in a via Fernando Gonzalez 2001-01-09
6136720 Plasma processing tools dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers Kevin G. Donohoe 2000-10-24
6136767 Dilute composition cleaning method Max Hineman 2000-10-24
6136670 Semiconductor processing methods of forming contacts between electrically conductive materials Max Hineman 2000-10-24
6132552 Method and apparatus for controlling the temperature of a gas distribution plate in a process reactor Kevin G. Donohoe 2000-10-17
6121671 Semiconductor device having a substrate, an undoped silicon oxide structure, and an overlying doped silicon oxide structure with a side wall terminating at the undoped silicon oxide structure Kei-Yu Ko, Li Li 2000-09-19
6117791 Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby Kei-Yu Ko, Li Li 2000-09-12
6114252 Plasma processing tools, dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers Kevin G. Donohoe 2000-09-05
6111264 Small pores defined by a disposable internal spacer for use in chalcogenide memories Graham R. Wolstenholme, Steven T. Harshfield, Raymond A. Turi, Fernando Gonzalez, Donwon Park 2000-08-29
6095159 Method of modifying an RF circuit of a plasma chamber to increase chamber life and process capabilities Kevin G. Donohoe 2000-08-01
6080672 Self-aligned contact formation for semiconductor devices Werner Juengling, Kirk D. Prall, Trung T. Doan, David Dickerson, David S. Becker 2000-06-27
6080675 Method for cleaning waste matter from the backside of a semiconductor wafer substrate Kirk D. Prall 2000-06-27
6074953 Dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers Kevin G. Donohoe 2000-06-13
6066559 Method for forming a semiconductor connection with a top surface having an enlarged recess Fernando Gonzalez, Kirk D. Prall 2000-05-23
6062133 Global planarization method and apparatus 2000-05-16