Issued Patents All Time
Showing 25 most recent of 314 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9293185 | Apparatus including a capacitor-less memory cell and related methods | Chandra Mouli | 2016-03-22 |
| 9129847 | Transistor structures and integrated circuitry comprising an array of transistor structures | — | 2015-09-08 |
| 8872219 | Multi-dimensional solid state lighting device array system and associated methods and structures | Alan Mondada, Willard L. Hofer | 2014-10-28 |
| 8724372 | Capacitor-less memory cell, device, system and method of making same | Chandra Mouli | 2014-05-13 |
| 8643110 | Localized biasing for silicon on insulator structures | John K. Zahurak | 2014-02-04 |
| 8582350 | Capacitor-less memory cell, device, system and method of making same | Chandra Mouli | 2013-11-12 |
| 8551823 | Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines | — | 2013-10-08 |
| 8501509 | Multi-dimensional solid state lighting device array system and associated methods and structures | Alan Mondada, Willard L. Hofer | 2013-08-06 |
| 8501602 | Method of manufacturing devices having vertical junction edge | Chandra Mouli | 2013-08-06 |
| 8451650 | Capacitor-less memory cell, device, system and method of making same | Chandra Mouli | 2013-05-28 |
| 8374037 | Method for programming a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell | Parag Banerjee, Terry Gafron | 2013-02-12 |
| 8203866 | Capacitor-less memory cell, device, system and method of making same | Chandra Mouli | 2012-06-19 |
| 8173517 | Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure | David L. Chapek, Randhir P. S. Thakur | 2012-05-08 |
| 8159014 | Localized biasing for silicon on insulator structures | John K. Zahurak | 2012-04-17 |
| 8124491 | Container capacitor structure and method of formation thereof | D. Mark Durcan, Trung T. Doan, Roger Lee | 2012-02-28 |
| 8084322 | Method of manufacturing devices having vertical junction edge | Chandra Mouli | 2011-12-27 |
| 8034716 | Semiconductor structures including vertical diode structures and methods for making the same | Tyler Lowrey, Trung T. Doan, Raymond A. Turi, Graham R. Wolstenholme | 2011-10-11 |
| 8022385 | Memory devices with buried lines | Gurtej S. Sandhu, Mike Violette | 2011-09-20 |
| 7995402 | Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell | Parag Banerjee, Terry Gafron | 2011-08-09 |
| 7919800 | Capacitor-less memory cells and cell arrays | Chandra Mouli | 2011-04-05 |
| 7852668 | Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell | Parag Banerjee, Terry Gafron | 2010-12-14 |
| 7804139 | Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench | Chandra Mouli | 2010-09-28 |
| 7749860 | Method for forming a self-aligned T-shaped isolation trench | David L. Chapek, Ranshir P. S. Thakur | 2010-07-06 |
| 7678678 | Method to chemically remove metal impurities from polycide gate sidewalls | Don Powell | 2010-03-16 |
| 7659152 | Localized biasing for silicon on insulator structures | John K. Zahurak | 2010-02-09 |