Issued Patents All Time
Showing 26–50 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9915702 | Channel sharing for testing circuits having non-identical cores | Yu Huang, Mark Kassab, Wu-Tung Cheng, Jay Babak Jahangiri | 2018-03-13 |
| 9874606 | Selective per-cycle masking of scan chains for system level test | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee | 2018-01-23 |
| 9778316 | Multi-stage test response compactors | Jerzy Tyszer, Grzegorz Mrugalski, Mark Kassab, Wu-Tung Cheng | 2017-10-03 |
| 9720041 | Scan-based test architecture for interconnects in stacked designs | Jerzy Tyszer | 2017-08-01 |
| 9720040 | Timing-aware test generation and fault simulation | Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang | 2017-08-01 |
| 9714981 | Test-per-clock based on dynamically-partitioned reconfigurable scan chains | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski | 2017-07-25 |
| 9651622 | Isometric test compression with low toggling activity | Amit Amar Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer +1 more | 2017-05-16 |
| 9568552 | Logic built-in self-test with high test coverage and low switching activity | Xijiang Lin | 2017-02-14 |
| 9377508 | Selective per-cycle masking of scan chains for system level test | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer | 2016-06-28 |
| 9347993 | Test generation for test-per-clock | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski | 2016-05-24 |
| 9335377 | Test-per-clock based on dynamically-partitioned reconfigurable scan chains | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski | 2016-05-10 |
| 9335374 | Dynamic shift for test pattern compression | Xijiang Lin, Mark Kassab | 2016-05-10 |
| 9250287 | On-chip comparison and response collection tools and techniques | Nilanjan Mukherjee, Jerzy Tyszer | 2016-02-02 |
| 9134370 | Continuous application and decompression of test patterns and selective compaction of test responses | Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee | 2015-09-15 |
| 9088522 | Test scheduling with pattern-independent test access mechanism | Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Jakub Janicki, Jerzy Tyszer +1 more | 2015-07-21 |
| 9086454 | Timing-aware test generation and fault simulation | Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang | 2015-07-21 |
| 9009553 | Scan chain configuration for test-per-clock based on circuit topology | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski | 2015-04-14 |
| 9003248 | Fault-driven scan chain configuration for test-per-clock | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski | 2015-04-07 |
| 8996941 | Test data volume reduction based on test cube properties | Xijiang Lin | 2015-03-31 |
| 8914694 | On-chip comparison and response collection tools and techniques | Nilanjan Mukherjee, Jerzy Tyszer | 2014-12-16 |
| 8890563 | Scan cell use with reduced power consumption | Xijiang Lin | 2014-11-18 |
| 8832512 | Low power compression of incompatible test cubes | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Przemyslaw Szczerbicki, Jerzy Tyszer | 2014-09-09 |
| 8726112 | Scan test application through high-speed serial input/outputs | Nilanjan Mukherjee, Mark Kassab, Thomas Hans Rinderknecht, Mohamed Dessouky | 2014-05-13 |
| 8726113 | Selective per-cycle masking of scan chains for system level test | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer | 2014-05-13 |
| 8683280 | Test generator for low power built-in self-test | Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie | 2014-03-25 |