Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773793 | Transistor performance modification with stressor structures | Scott R. Summerfelt, Rajni J. Aggarwal | 2017-09-26 |
| 9608109 | N-channel demos device | Chin-Yu Tsai, Imran Khan | 2017-03-28 |
| 9577094 | Low cost demos transistor with improved CHC immunity | Amitava Chatterjee, Imran Khan, Kaiping Liu | 2017-02-21 |
| 9202912 | Low cost demos transistor with improved CHC immunity | Amitava Chatterjee, Imran Khan, Kaiping Liu | 2015-12-01 |
| 8530298 | Radiation hardened integrated circuit | Richard Guerra Roybal, Shariq Arshad, James Fred Salzman | 2013-09-10 |
| 7795085 | Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs | Jong Shik Yoon, Amitava Chatterjee, Kayvan Sadra | 2010-09-14 |
| 7736983 | High threshold NMOS source-drain formation with As, P and C to reduce damage | Puneet Kohli, Manoj Mehrotra | 2010-06-15 |
| 7691700 | Multi-stage implant to improve device characteristics | Manoj Mehrotra, Stan Ashburn | 2010-04-06 |
| 7662690 | Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells | Zhiqiang Wu | 2010-02-16 |
| 7601575 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | Haowen Bu, Shashank S. Ekbote, Rajesh Khamankar, Freidoon Mehrad | 2009-10-13 |
| 7216310 | Design method and system for optimum performance in integrated circuits that use power management | Amitava Chatterjee, David B. Scott, Theodore W. Houston, Song Zhao, Zhiqiang Wu | 2007-05-08 |
| 7045436 | Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) | Amitava Chatterjee, Alwin Tsao, Manuel Quevedo-Lopez, Jong Shik Yoon | 2006-05-16 |
| 6933203 | Methods for improving well to well isolation | Zhiqiang Wu, Jau-Yuann Yang | 2005-08-23 |
| 6930007 | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance | Haowen Bu, Shashank S. Ekbote, Rajesh Khamankar, Freidoon Mehrad | 2005-08-16 |
| 6855984 | Process to reduce gate edge drain leakage in semiconductor devices | Zhiqiang Wu, Song Zhao | 2005-02-15 |
| 6794730 | High performance PNP bipolar device fully compatible with CMOS process | Youngmin Kim, Seetharaman Sridhar, Amitava Chatterjee | 2004-09-21 |
| 6462931 | High-dielectric constant capacitor and memory | John Mark Anthony, Scott R. Summerfelt | 2002-10-08 |
| 5830532 | Method to produce ultrathin porous silicon-oxide layer | Robert M. Wallace, Yi Wei | 1998-11-03 |