NL

Nace Layadi

AS Agere Systems: 10 patents #101 of 1,849Top 6%
AG Agere Systems Guardian: 10 patents #15 of 810Top 2%
AT AT&T: 3 patents #5,550 of 18,772Top 30%
CM Chartered Semiconductor Manufacturing: 3 patents #194 of 840Top 25%
EL Elith: 1 patents #5 of 14Top 40%
Overall (All Time): #156,235 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 25 most recent of 26 patents

Patent #TitleCo-InventorsDate
7163438 Zone polishing using variable slurry solid content Alvaro Maury, Jovin Lim, Sebastian Ouek 2007-01-16
6984166 Zone polishing using variable slurry solid content Alvaro Maury, Jovin Lim, Sebastian Ser Wee Quek 2006-01-10
6977128 Multi-layered semiconductor structure David M. Boulin, Reginald Conway Farrow, Isik C. Kizilyalli, Masis Mkrtchyan 2005-12-20
6910907 Contact for use in an integrated circuit and a method of manufacture therefor Alvaro Maury 2005-06-28
6821886 IMP TiN barrier metal process Alvaro Maury, Jovin Lim 2004-11-23
6730600 Method of dry etching a semiconductor device in the absence of a plasma Simon John Molloy, Sailesh Mansinh Merchant, Isik C. Kizilyalli 2004-05-04
6727588 Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics Mahjoub Ali Abdelgadir, Sailesh Mansinh Merchant, Vivek Saxena, Pei H. Yih 2004-04-27
6720604 Capacitor for an integrated circuit Larry Bruce Fritzinger, Sailesh Mansinh Merchant, Pradip K. Roy 2004-04-13
6706609 Method of forming an alignment feature in or on a multi-layered semiconductor structure David M. Boulin, Reginald Conway Farrow, Isik C. Kizilyalli, Masis Mkrtchyan 2004-03-16
6656850 Method for in-situ removal of side walls in MOM capacitor formation Simon John Molloy, Edward B. Harris, Sidhartha Sen 2003-12-02
6585830 Method for cleaning tungsten from deposition wall chambers Sailesh Mansinh Merchant, Simon John Molloy 2003-07-01
6576529 Method of forming an alignment feature in or on a multilayered semiconductor structure David M. Boulin, Reginald Conway Farrow, Isik C. Kizilyalli, Masis Mkrtchyan 2003-06-10
6548906 Method for reducing a metal seam in an interconnect structure and a device manufactured thereby Alvaro Maury 2003-04-15
6472307 Methods for improved encapsulation of thick metal features in integrated circuit fabrication Donald C. Dennis, Simon John Molloy, Kurt G. Steiner, Sylvia Thomas 2002-10-29
6458648 Method for in-situ removal of side walls in MOM capacitor formation Simon John Molloy, Edward B. Harris, Sidhartha Sen 2002-10-01
6436829 Two phase chemical/mechanical polishing process for tungsten layers Arun K. Nanda 2002-08-20
6406999 Semiconductor device having reduced line width variations between tightly spaced and isolated features Thomas Craig Esry, Sylvia Marci Luque, Simon John Molloy, Mario Pita 2002-06-18
6395639 Process for improving line width variations between tightly spaced and isolated features in integrated circuits Thomas Craig Esry, Sylvia Marci Luque, Simon John Molloy, Mario Pita 2002-05-28
6358790 Method of making a capacitor Larry Bruce Fritzinger, Sailesh Mansinh Merchant, Pradip K. Roy 2002-03-19
6323537 Capacitor for an integrated circuit Larry Bruce Fritzinger, Sailesh Mansinh Merchant, Pradip K. Roy 2001-11-27
6258610 Method analyzing a semiconductor surface using line width metrology with auto-correlation operation James Walter Blatchford, Scott Jessen, Brittin Kane, John M. McIntosh, Simon John Molloy 2001-07-10
6249016 Integrated circuit capacitor including tapered plug Samir Chaudhry, Sundar Srinivasan Chetlur, Pradip K. Roy, Hem M. Vaidya 2001-06-19
6218085 Process for photoresist rework to avoid sodium incorporation Simon John Molloy, Allen Yen, Brian D. Crevasse, Steven Alan Lytle 2001-04-17
6218255 Method of making a capacitor Larry Bruce Fritzinger, Sailesh Mansinh Merchant, Pradip K. Roy 2001-04-17
6204186 Method of making integrated circuit capacitor including tapered plug Samir Chaudhry, Sundar Srinivasan Chetlur, Pradip K. Roy, Hem M. Vaidya 2001-03-20