MK

Mark W. Kuemerle

IBM: 11 patents #9,995 of 70,183Top 15%
Globalfoundries: 10 patents #365 of 4,424Top 9%
Disney: 4 patents #1,638 of 6,686Top 25%
GU Globalfoundries U.S.: 1 patents #22 of 211Top 15%
Overall (All Time): #152,298 of 4,157,543Top 4%
26
Patents All Time

Issued Patents All Time

Showing 25 most recent of 26 patents

Patent #TitleCo-InventorsDate
12095494 Lateral escape using triangular structure of transceivers Aatreya Chakravarti, Wolfgang Sauter, Eric W. Tremble 2024-09-17
11282806 Partitioned substrates with interconnect bridge Wolfgang Sauter, Eric W. Tremble 2022-03-22
11037873 Hermetic barrier for semiconductor device Nicholas A. Polomoff, Igor Arsovski 2021-06-15
10748852 Multi-chip module (MCM) with chip-to-chip connection redundancy and method Wolfgang Sauter, Edmund Blackshear 2020-08-18
10714411 Interconnected integrated circuit (IC) chip structure and packaging and method of forming same Wolfgang Sauter, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent +2 more 2020-07-14
10381304 Interconnect structure Luke England 2019-08-13
9875956 Integrated interface structure Wolfgang Sauter, Daniel P. Greenberg, Eric W. Tremble 2018-01-23
9870163 Double bandwidth algorithmic memory array Igor Arsovski, Eric D. Hunt-Schroeder 2018-01-16
9865486 Timing/power risk optimized selective voltage binning using non-linear voltage slope Igor Arsovski, Jeanne P. Bickford, Susan K. Lichtensteiger, Jeanne H. Raymond 2018-01-09
9619609 Integrated circuit chip design methods and systems using process window-aware timing analysis Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger, Jeffrey G. Hemmett 2017-04-11
9552447 Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger 2017-01-24
9501607 Composite views for IP blocks in ASIC designs Igor Arsovski, Qing Li 2016-11-22
9372520 Reverse performance binning Paul S. Zuchowski 2016-06-21
9269407 System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger 2016-02-23
9171125 Limiting skew between different device types to meet performance requirements of an integrated circuit Igor Arsovski, Jeanne P. Bickford 2015-10-27
8963620 Controlling circuit voltage and frequency based upon location-dependent temperature Jeanne P. Bickford, Eric A. Foreman, David J. Hathaway, Susan K. Lichtensteiger 2015-02-24
8843874 Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger 2014-09-23
8839170 Power/performance optimization through temperature/voltage control Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger 2014-09-16
8839165 Power/performance optimization through continuously variable temperature-based voltage control Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger 2014-09-16
8543960 Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures Jeanne P. Bickford, Eric A. Foreman, Susan K. Lichtensteiger 2013-09-24
8300752 Method, circuit, and design structure for capturing data across a pseudo-synchronous interface Malede W. Berhanu, Christopher D. Hanudel, David W. Milton, Clarence R. Ogilvie, Jack R. Smith 2012-10-30
8189723 Method, circuit, and design structure for capturing data across a pseudo-synchronous interface Malede W. Berhanu, Christopher D. Hanudel, David W. Milton, Clarence R. Ogilvie, Jack R. Smith 2012-05-29
7529962 System for expanding a window of valid data Malede W. Berhanu, Christopher D. Hanudel, David W. Milton, Clarence R. Ogilvie, Jack R. Smith 2009-05-05
7475366 Integrated circuit design closure method for selective voltage binning Susan K. Lichtensteiger, Douglas W. Stout, Ivan L. Wemple 2009-01-06
6457131 System and method for power optimization in parallel units 2002-09-24