Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8312309 | Technique for promoting determinism among multiple clock domains | Eric L. Hendrickson, Sanjoy K. Mondal, William Hodges, Lance Hacking, Sankaran M. Menon | 2012-11-13 |
| 7216274 | Flexible scan architecture | Talal K. Jaber, Srinivas Patil, Chih-Jen Lin, Anil K. Sabbavarapu, David M. Wu +1 more | 2007-05-08 |
| 6901540 | TLB parity error recovery | T. W. Griffith, Jr. | 2005-05-31 |
| 6678807 | System and method for multiple store buffer forwarding in a system with a restrictive memory model | Bryan Boatright, Rajesh Patel | 2004-01-13 |
| 6658555 | Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline | James Allan Kahle, Hung Q. Le, Charles Roberts Moore, David Shippy | 2003-12-02 |
| 6611900 | System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model | Rajesh Patel, Bryan Boatright | 2003-08-26 |
| 6543002 | Recovery from hang condition in a microprocessor | James Allan Kahle, Hung Q. Le, Kevin F. Reick, David Shippy | 2003-04-01 |
| 6490653 | Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing system | Robert Alan Cargnoni, Bruce Joseph Ronchetti, David Shippy | 2002-12-03 |
| 6477635 | Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing | James Allan Kahle, George McNeil Lattimore, Jose Angel Paredes | 2002-11-05 |
| 6463511 | System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model | Bryan Boatright, Rajesh Patel | 2002-10-08 |
| 6425069 | Optimization of instruction stream execution that includes a VLIW dispatch group | John Edward Derrick | 2002-07-23 |
| 6338128 | System and method for invalidating an entry in a translation unit | Albert Chang, Edward John Silha, Gus Yeung | 2002-01-08 |
| 6336183 | System and method for executing store instructions | Hung Q. Le, Robert G. McDonald, David Shippy | 2002-01-01 |
| 6336168 | System and method for merging multiple outstanding load miss instructions | Marlin Wayne Frederick, Jr., Bruce Joseph Ronchetti, David Shippy | 2002-01-01 |
| 6301654 | System and method for permitting out-of-order execution of load and store instructions | Bruce Joseph Ronchetti, Dave Shippy | 2001-10-09 |
| 6298436 | Method and system for performing atomic memory accesses in a processor system | James Allan Kahle, Hung Q. Le, David Shippy | 2001-10-02 |
| 6289428 | Superscaler processor and method for efficiently recovering from misaligned data addresses | John Edward Derrick, Hung Q. Le, David Shippy | 2001-09-11 |
| 6266768 | System and method for permitting out-of-order execution of load instructions | Marlin Wayne Frederick, Jr., Bruce Joseph Ronchetti | 2001-07-24 |
| 6237081 | Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor | Hung Q. Le, Bruce Joseph Ronchetti, David Shippy | 2001-05-22 |
| 6085289 | Method and system for load data formatting and improved method for cache line organization | John Andrew Beck, Michael Kevin Ciraula | 2000-07-04 |
| 6079002 | Dynamic expansion of execution pipeline stages | John Stephen Muhich, Steven Wayne White, Troy N. Hicks | 2000-06-20 |
| 6021485 | Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching | Kurt A. Feiste, John Stephen Muhich, Steven Wayne White | 2000-02-01 |
| 6021467 | Apparatus and method for processing multiple cache misses to a single cache line | Brian R. Konigsburg, John Stephen Muhich, Steven Wayne White | 2000-02-01 |
| 5974259 | Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels | Humberto Felipe Casal, Kurt A. Feiste, T. W. Griffith, Jr. | 1999-10-26 |
| 5931957 | Support for out-of-order execution of loads and stores in a processor | Brian R. Konigsburg, John Stephen Muhich, Steven Wayne White | 1999-08-03 |