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Scan architecture and design methodology yielding significant reduction in scan area and power overhead |
Talal K. Jaber |
2012-11-27 |
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Common test logic for multiple operation modes |
Talal K. Jaber, Ming Zhang |
2010-06-08 |
| 7370249 |
Method and apparatus for testing a memory array |
Zhuoyu Bao, Chih-Jen Lin |
2008-05-06 |
| 7216274 |
Flexible scan architecture |
Talal K. Jaber, Srinivas Patil, Larry Edward Thatcher, Chih-Jen Lin, Anil K. Sabbavarapu +1 more |
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| 6815977 |
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Anil K. Sabbavarapu, Talal K. Jaber, Grant McFarland, Paven R. Sunkerneni |
2004-11-09 |
| 6795948 |
Weighted random pattern test using pre-stored weights |
Chih-Jen Lin |
2004-09-21 |
| 6683467 |
Method and apparatus for providing rotational burn-in stress testing |
Ali Keshavarzi, Yibin Ye, Vivek K. De |
2004-01-27 |
| 6311295 |
System and method for testing a clock signal |
Humberto Felipe Casal, Hehching Harry Li |
2001-10-30 |
| 5968194 |
Method for application of weighted random patterns to partial scan designs |
Praveen Parvathala, Naga Gollakota |
1999-10-19 |
| 5920489 |
Method and system for modeling the behavior of a circuit |
Michael Thomas Dibrino |
1999-07-06 |
| 5581699 |
System and method for testing a clock signal |
Humberto Felipe Casal, Hehching Harry Li |
1996-12-03 |
| 5299136 |
Fully testable DCVS circuits with single-track global wiring |
Jacquelin Babakanian, James W. Davis, Mark S. Garvin, Robert M. Swanson, Nandor G. Thoma |
1994-03-29 |
| 5272397 |
Basic DCVS circuits with dual function load circuits |
Imin P. Chen, James W. Davis, Robert M. Swanson, Nandor G. Thoma |
1993-12-21 |
| 5042034 |
By-pass boundary scan design |
Anthony Correale, Jr., Richard M. Doney, Kim E. O'Donnell, Andrew Kegl, Erwin A. Tate |
1991-08-20 |
