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USPTO Patent Rankings Data through Dec 31, 2025
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David M. Wu — 14 Patents

Intel: 8 patents #4,914 of 30,777Top 20%
IBM: 6 patents #16,491 of 70,183Top 25%
Melbourne, FL: #92 of 1,077 inventorsTop 9%
Florida: #3,685 of 67,251 inventorsTop 6%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
David M. Wu has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 1991 and the most recent in November 2012. David M. Wu ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list David M. Wu in Melbourne, FL, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8321730 Scan architecture and design methodology yielding significant reduction in scan area and power overhead Talal K. Jaber 2012-11-27 $12,455,000
7734972 Common test logic for multiple operation modes Talal K. Jaber, Ming Zhang 2010-06-08 $11,764,000
7370249 Method and apparatus for testing a memory array Zhuoyu Bao, Chih-Jen Lin 2008-05-06 $19,899,000
7216274 Flexible scan architecture Talal K. Jaber, Srinivas Patil, Larry Edward Thatcher, Chih-Jen Lin, Anil K. Sabbavarapu +1 more 2007-05-08 $17,693,000
6815977 Scan cell systems and methods Anil K. Sabbavarapu, Talal K. Jaber, Grant McFarland, Paven R. Sunkerneni 2004-11-09 $39,644,000
6795948 Weighted random pattern test using pre-stored weights Chih-Jen Lin 2004-09-21 $17,403,000
6683467 Method and apparatus for providing rotational burn-in stress testing Ali Keshavarzi, Yibin Ye, Vivek K. De 2004-01-27 $81,098,000
6311295 System and method for testing a clock signal Humberto Felipe Casal, Hehching Harry Li 2001-10-30 $34,081,000
5968194 Method for application of weighted random patterns to partial scan designs Praveen Parvathala, Naga Gollakota 1999-10-19 $212,976,000
5920489 Method and system for modeling the behavior of a circuit Michael Thomas Dibrino 1999-07-06 $40,075,000
5581699 System and method for testing a clock signal Humberto Felipe Casal, Hehching Harry Li 1996-12-03 $20,817,000
5299136 Fully testable DCVS circuits with single-track global wiring Jacquelin Babakanian, James W. Davis, Mark S. Garvin, Robert M. Swanson, Nandor G. Thoma 1994-03-29 $7,345,000
5272397 Basic DCVS circuits with dual function load circuits Imin P. Chen, James W. Davis, Robert M. Swanson, Nandor G. Thoma 1993-12-21 $18,906,000
5042034 By-pass boundary scan design Anthony Correale, Jr., Richard M. Doney, Kim E. O'Donnell, Andrew Kegl, Erwin A. Tate 1991-08-20 $42,010,000