Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6642802 | Ring oscillator providing single event transient immunity | Kenneth R. Knowles | 2003-11-04 |
| 6487134 | Single-event upset tolerant latch for sense amplifiers | Scott Doyle | 2002-11-26 |
| 5822596 | Controlling power up using clock gating | Humberto Felipe Casal, Hehching Harry Li, Trong D. Nguyen | 1998-10-13 |
| 5732233 | High speed pipeline method and apparatus | Peter Juergen Klim | 1998-03-24 |
| 5672991 | Differential delay line circuit for outputting signal with equal pulse widths | Trong D. Nguyen | 1997-09-30 |
| 5619158 | Hierarchical clocking system using adaptive feedback | Humberto Felipe Casal, Joel Roger Davidson, Hehching Harry Li, Yuan-Chang Lo, Trong D. Nguyen +1 more | 1997-04-08 |
| 5539333 | CMOS receiver circuit | Tai A. Cao, Satyajit Dutta, Thai Nguyen, Thanh D. Trinh | 1996-07-23 |
| 5525914 | CMOS driver circuit | Tai A. Cao, Satyajit Dutta, Thai Nguyen, Thanh D. Trinh | 1996-06-11 |
| 5524035 | Symmetric clock system for a data processing system including dynamically switchable frequency divider | Humberto Felipe Casal, Rafey Mahmud, Trong D. Nguyen, Mark L. Shulman | 1996-06-04 |
| 5442776 | Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system | Robert P. Masleid | 1995-08-15 |
| 5299136 | Fully testable DCVS circuits with single-track global wiring | Jacquelin Babakanian, James W. Davis, Mark S. Garvin, Robert M. Swanson, David M. Wu | 1994-03-29 |
| 5272397 | Basic DCVS circuits with dual function load circuits | Imin P. Chen, James W. Davis, Robert M. Swanson, David M. Wu | 1993-12-21 |
| 5166547 | Programmable DCVS logic circuits | Jacquelin Babakanian, James W. Davis, Mark S. Garvin, Kim P. Liew, Yoav Medan | 1992-11-24 |
| 4947369 | Microword generation mechanism utilizing a separate branch decision programmable logic array | Victor S. Moore, Wayne R. Kraft | 1990-08-07 |
| 4608649 | Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design | James W. Davis, Victor S. Moore | 1986-08-26 |
| 4583193 | Integrated circuit mechanism for coupling multiple programmable logic arrays to a common bus | Wayne R. Kraft, Moises Cases, William L. Stahl, Jr., Virgil D. Wyatt | 1986-04-15 |
| 4575794 | Clocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unit | Gerard A. Veneski, Moises Cases | 1986-03-11 |
| 4567561 | Large scale integration data processor signal transfer mechanism | Virgil D. Wyatt, Wayne R. Kraft | 1986-01-28 |
| 4531068 | Bus line precharging tristate driver circuit | Wayne R. Kraft, Victor S. Moore, William L. Stahl, Jr. | 1985-07-23 |
| 4500800 | Logic performing cell for use in array structures | Moises Cases, Wayne R. Kraft, William L. Stahl, Jr. | 1985-02-19 |
| 4488067 | Tristate driver circuit with low standby power consumption | Wayne R. Kraft, Victor S. Moore, William L. Stahl, Jr. | 1984-12-11 |
| 4484268 | Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays | Victor S. Moore, Wayne R. Kraft | 1984-11-20 |
| 4395646 | Logic performing cell for use in array structures | Moises Cases, Wayne R. Kraft, Victor S. Moore, William L. Stahl, Jr. | 1983-07-26 |
| 4364074 | V-MOS Device with self-aligned multiple electrodes | Richard R. Garnache, Donald M. Kenney | 1982-12-14 |