KN

Khanh B. Nguyen

AM AMD: 34 patents #265 of 9,279Top 3%
EL Euv Llc.: 1 patents #33 of 57Top 60%
Overall (All Time): #99,427 of 4,157,543Top 3%
35
Patents All Time

Issued Patents All Time

Showing 25 most recent of 35 patents

Patent #TitleCo-InventorsDate
6875668 Notched gate structure fabrication Scott A. Bell 2005-04-05
6740566 Ultra-thin resist shallow trench process using high selectivity nitride etch Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Fei Wang, Chih-Yuh Yang 2004-05-25
6544885 Polished hard mask process for conductor layer patterning Harry J. Levinson, Christopher F. Lyons, Scott A. Bell, Fei Wang, Chih-Yuh Yang 2003-04-08
6492067 Removable pellicle for lithographic mask protection and handling Leonard E. Klebanoff, Daniel J. Rader, Scott D. Hector, Richard H. Stulen 2002-12-10
6440640 Thin resist with transition metal hard mask for via etch application Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Fei Wang, Scott A. Bell 2002-08-27
6414326 Technique to separate dose-induced vs. focus-induced CD or linewidth variation 2002-07-02
6370680 Device to determine line edge roughness effect on device performance 2002-04-09
6326319 Method for coating ultra-thin resist films Christopher Lee Pike, Christopher F. Lyons 2001-12-04
6316277 Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist in DUV lithography Khoi A. Phan, Christopher F. Lyons, Jeff Schefske 2001-11-13
6309926 Thin resist with nitride hard mask for gate etch application Scott A. Bell, Christopher F. Lyons, Harry J. Levinson, Fei Wang, Chih-Yuh Yang 2001-10-30
6306560 Ultra-thin resist and SiON/oxide hard mask for metal etch Fei Wang, Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang 2001-10-23
6271602 Method for reducing the susceptibility to chemical-mechanical polishing damage of an alignment mark formed in a semiconductor substrate Paul Ackmann, Richard D. Edwards, Stuart E. Brown 2001-08-07
6255125 Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer Regina Tien Schmidt, Christopher A. Spence, Anna M. Minvielle, Marina V. Plat 2001-07-03
6208747 Determination of scanning error in scanner by reticle rotation Harry J. Levinson 2001-03-27
6207966 Mark protection with transparent film Harry J. Levinson, Richard D. Edwards, Stuart E. Brown, Paul Ackmann 2001-03-27
6200907 Ultra-thin resist and barrier metal/oxide hard mask for metal etch Fei Wang, Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang 2001-03-13
6184128 Method using a thin resist mask for dual damascene stop layer etch Fei Wang, Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang 2001-02-06
6178256 Removal of reticle effect on critical dimension by reticle rotation Paul Ackmann, Stuart E. Brown 2001-01-23
6178221 Lithography reflective mask Harry J. Levinson 2001-01-23
6171763 Ultra-thin resist and oxide/nitride hard mask for metal etch Fei Wang, Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang 2001-01-09
6165695 Thin resist with amorphous silicon hard mask for via etch application Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Fei Wang, Scott A. Bell 2000-12-26
6162587 Thin resist with transition metal hard mask for via etch application Chih-Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Fei Wang, Scott A. Bell 2000-12-19
6159643 Extreme ultraviolet lithography reflective mask Harry J. Levinson 2000-12-12
6156658 Ultra-thin resist and silicon/oxide hard mask for metal etch Fei Wang, Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Chih-Yuh Yang 2000-12-05
6140023 Method for transferring patterns created by lithography Harry J. Levinson, Scott A. Bell, Christopher F. Lyons, Fei Wang, Chih-Yuh Yang 2000-10-31