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Wafer handler and methods of manufacture |
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2018-08-14 |
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Wafer handler and methods of manufacture |
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2017-04-04 |
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Reduction of edge chipping during wafer handling |
Sarah H. Knickerbocker |
2014-08-19 |
| 8753460 |
Reduction of edge chipping during wafer handling |
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2014-06-17 |
| 8314500 |
Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers |
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Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers |
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Forming robust solder interconnect structures by reducing effects of seed layer underetching |
Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quinn +3 more |
2010-08-03 |
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Method of forming a bond pad on an I/C chip and resulting structure |
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| 7473997 |
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching |
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Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer |
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2006-12-05 |
| 6995084 |
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching |
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2006-02-07 |
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I/C chip suitable for wire bonding |
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Barrier for interconnect and method |
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Reactive Ion Etching chamber design for flip chip interconnections |
Kamalesh K. Srivastava, Peter C. Wade, William Brearley |
2003-03-11 |
| 6293457 |
Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization |
Kamalesh K. Srivastava, Mary Cullinan-Scholl, William Brearley, Peter C. Wade |
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2001-05-08 |
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Methods and apparatus for relieving stress and resisting stencil delamination when performing lift-off processes that utilize high stress metals and/or multiple evaporation steps |
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1994-01-11 |
| 4588471 |
Process for etching composite chrome layers |
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1986-05-13 |
