GM

Guarionex Morales

AM AMD: 22 patents #477 of 9,279Top 6%
Overall (All Time): #186,689 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6500757 Method and apparatus for controlling grain growth roughening in conductive stacks Jeffrey A. Shields 2002-12-31
6444593 Surface treatment of low-K SiOF to prevent metal interaction Minh Van Ngo, Richard J. Huang 2002-09-03
6436850 Method of degassing low k dielectric for metal deposition 2002-08-20
6420104 Method of reducing contact size by spacer filling Bharath Rangarajan, Stephen Keetai Park 2002-07-16
6380556 Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure David Bang, Takeshi Nogami, Shekhar Pramanick 2002-04-30
6335273 Surface treatment of low-K SiOF to prevent metal interaction Richard J. Huang, Simon S. Chan 2002-01-01
6335533 Electron microscopy sample having silicon nitride passivation layer Dawn Hopper, Lu You 2002-01-01
6281584 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces Minh Van Ngo, Richard J. Huang 2001-08-28
6281121 Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal Dirk Brown, Takeshi Nogami 2001-08-28
6265273 Method of forming rectangular shaped spacers Steven C. Avanzino, Stephen Keetai Park, Bharath Rangarajan, Jeffrey A. Shields, Larry Wang 2001-07-24
6265294 Integrated circuit having double bottom anti-reflective coating layer Stephen Keetai Park, Bharath Rangarajan, Jeff Shields 2001-07-24
6235632 Tungsten plug formation Takeshi Nogami, Minh Van Ngo 2001-05-22
6211074 Methods and arrangements for reducing stress and preventing cracking in a silicide layer Richard J. Huang 2001-04-03
6177345 Method of silicide film formation onto a semiconductor substrate Jianshi Wang, Judith Quan Rizzuto, Hao Fang 2001-01-23
6127193 Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure David Bang, Takeshi Nogami, Shekhar Pramanick 2000-10-03
6110829 Ultra-low temperature Al fill for sub-0.25 .mu.m generation of ICs using an Al-Ge-Cu alloy Paul R. Besser, Robin Cheung 2000-08-29
6100192 Method of forming high integrity tungsten silicide thin films Richard J. Huang 2000-08-08
6096648 Copper/low dielectric interconnect formation with reduced electromigration Sergey Lopatin, Takeshi Nogami, Robin Cheung, Christy Mei-Chu Woo 2000-08-01
6083817 Cobalt silicidation using tungsten nitride capping layer Takeshi Nogami, Robert Chen 2000-07-04
6046106 High density plasma oxide gap filled patterned metal layers with improved electromigration resistance Khanh Tran, Paul R. Besser, Shekhar Pramanick 2000-04-04
6033584 Process for reducing copper oxide during integrated circuit fabrication Minh Van Ngo, Takeshi Nogami 2000-03-07
6030891 Vacuum baked HSQ gap fill layer for high integrity borderless vias Khanh Tran, Richard J. Huang 2000-02-29
5994778 Surface treatment of low-k SiOF to prevent metal interaction Richard J. Huang, Simon S. Chan 1999-11-30