AM

Anthony Mowry

Globalfoundries: 16 patents #218 of 4,424Top 5%
AM AMD: 7 patents #1,662 of 9,279Top 20%
Overall (All Time): #185,388 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8796807 Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials Rolf Stephan, Markus Forsberg, Gert Burbach 2014-08-05
8665592 Heat management using power management information David Gerald Farber, Michael J. Austin, John E. Moore, Jr. 2014-03-04
8564120 Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside David Gerald Farber, Fred N. Hause, Markus Lenski 2013-10-22
8530894 Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions Casey Scott, Vassilios Papageorgiou, Andy Wei, Markus Lenski, Andreas Gehring 2013-09-10
8507351 Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation Markus Lenski, Guido Koerner, Ralf Otterbach 2013-08-13
8373244 Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure Casey Scott, Roman Boschke 2013-02-12
8227266 Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions Casey Scott, Vassilios Papageorgiou, Andy Wei, Markus Lenski, Andreas Gehring 2012-07-24
8212184 Cold temperature control in a semiconductor device Casey Scott, Maciej Wiatr, Ralf Richter 2012-07-03
8129236 Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode Andreas Gehring, Andy Wei 2012-03-06
8093634 In situ formed drain and source regions in a silicon/germanium containing transistor device Andy Wei, Andreas Gehring, Casey Scott 2012-01-10
8064197 Heat management using power management information David Gerald Farber, Michael J. Austin, John E. Moore, Jr. 2011-11-22
8048330 Method of forming an interlayer dielectric material having different removal rates during CMP Ralf Richter, Thomas Foltyn 2011-11-01
7977179 Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation Markus Lenski, Guido Koerner, Ralf Otterbach 2011-07-12
7939399 Semiconductor device having a strained semiconductor alloy concentration profile Bernhard Trui, Maciej Wiatr, Andreas Gehring, Andy Wei 2011-05-10
7923338 Increasing stress transfer efficiency in a transistor by reducing spacer width during the drain/source implantation sequence Maciej Wiatr, Roman Boschke 2011-04-12
7906385 Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps Markus Lenski, Frank Wirbeleit 2011-03-15
7879667 Blocking pre-amorphization of a gate electrode of a transistor Markus Lenski, Andy Wei, Roman Boschke 2011-02-01
7811876 Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device Casey Scott, Frank Wirbeleit 2010-10-12
7790537 Method for creating tensile strain by repeatedly applied stress memorization techniques Andy Wei, Andreas Gehring, Maciej Wiatr 2010-09-07
7772077 Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region Andreas Gehring, Andy Wei, Manuj Rathor 2010-08-10
7745337 Method of optimizing sidewall spacer size for silicide proximity with in-situ clean David Gerald Farber, Fred N. Hause, Markus Lenski 2010-06-29
7741663 Air gap spacer formation Fred N. Hause, David Gerald Farber, Markus Lenski 2010-06-22
7713763 Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions Casey Scott, Vassilios Papageorgiou, Andy Wei, Markus Lenski, Andreas Gehring 2010-05-11