Issued Patents All Time
Showing 25 most recent of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11490812 | Systems and methods for monitoring and detecting symptoms of infectious conditions | — | 2022-11-08 |
| 9495491 | Reliability aware thermal design | Kingsuk Maitra, Tung Thanh Nguyen, Brian K. Langendorf, Julia Purtell, Rune Hartung Jensen +1 more | 2016-11-15 |
| 8501504 | Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer | Kok Yong Yiang, Rick Francis, Van-Hung Pham | 2013-08-06 |
| 8022716 | Dielectric breakdown lifetime enhancement using alternating current (AC) capacitance | Kok Yong Yiang, Rick Francis, Van-Hung Pham | 2011-09-20 |
| 7755194 | Composite barrier layers with controlled copper interface surface roughness | Connie P. Wang, Christy Mei-Chu Woo, Paul L. King | 2010-07-13 |
| 7451411 | Integrated circuit design system | Christine Hau-Riege | 2008-11-11 |
| 7379924 | Quantifying and predicting the impact of line edge roughness on device reliability and performance | Calvin T. Gabriel | 2008-05-27 |
| 7340360 | Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness | John H. Zhang, Kurt Taylor, Eugene Zhao, Rolf Geilenkeuser, Joerg-Oliver Weidner | 2008-03-04 |
| 7310155 | Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures | Luigi Capodieci, Bhanwar Singh, Ramkumar Subramanian | 2007-12-18 |
| 7288782 | Use of Ta-capped metal line to improve formation of memory element films | Steven C. Avanzino | 2007-10-30 |
| 7155359 | Determination of device failure characteristic | Hyeon-Seag Kim, Kurt Taylor | 2006-12-26 |
| 7146588 | Predicting EM reliability by decoupling extrinsic and intrinsic sigma | Darrell M. Erb | 2006-12-05 |
| 7084062 | Use of Ta-capped metal line to improve formation of memory element films | Steven C. Avanzino | 2006-08-01 |
| 7033940 | Method of forming composite barrier layers with controlled copper interface surface roughness | Connie P. Wang, Christy Mei-Chu Woo, Paul L. King | 2006-04-25 |
| 7026225 | Semiconductor component and method for precluding stress-induced void formation in the semiconductor component | Christine Hau-Riege, John Sanchez | 2006-04-11 |
| 6952052 | Cu interconnects with composite barrier layers for wafer-to-wafer uniformity | Connie P. Wang, Christy Mei-Chu Woo | 2005-10-04 |
| 6939803 | Method for forming conductor reservoir volume for integrated circuit interconnects | Pin-Chin Connie Wang, Christy Mei-Chu Woo | 2005-09-06 |
| 6897476 | Test structure for determining electromigration and interlayer dielectric failure | Hyeon-Seag Kim, Seung-Hyun Rhee, Christine Hau-Riege | 2005-05-24 |
| 6867056 | System and method for current-enhanced stress-migration testing of interconnect | Christine Hau-Riege | 2005-03-15 |
| 6858511 | Method of semiconductor via testing | — | 2005-02-22 |
| 6856160 | Maximum VCC calculation method for hot carrier qualification | Hyeon-Seag Kim, Nian Yang, Tien-Chun Yang | 2005-02-15 |
| 6825684 | Hot carrier oxide qualification method | Hyeon-Seag Kim, Nian Yang, Tien-Chun Yang | 2004-11-30 |
| 6822437 | Interconnect test structure with slotted feeder lines to prevent stress-induced voids | Christine Hau-Riege, John Sanchez | 2004-11-23 |
| 6822473 | Determination of permeability of layer material within interconnect | Christine Hau-Riege, Stefan Hau-Riege | 2004-11-23 |
| 6770847 | Method and system for Joule heating characterization | Huade Walter Yao, Van-Hung Pham | 2004-08-03 |