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Pin cloning and subway creation on automatically generated design physical hierarchy |
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Lateral castout (LCO) of victim cache line in data-invalid state |
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Soft hierarchy-based physical synthesis for large-scale, high-performance circuits |
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Empirically based dynamic control of acceptance of victim cache lateral castouts |
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Lateral cache-to-cache cast-in |
Guy L. Guthrie, Michael S. Siegel, William J. Starke, Derek E. Williams, Phillip G. Williams |
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| 8171448 |
Structure for a livelock resolution circuit |
Charles Ray Johns, David J. Krolak, Peichun Peter Liu |
2012-05-01 |
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Structure for dynamic livelock resolution with variable delay memory access queue |
Ronald P. Hall, Michael L. Karm, Todd A. Venton |
2012-03-06 |
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Livelock resolution |
Charles Ray Johns, David J. Krolak, Peichun Peter Liu |
2010-12-28 |
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Takuya Kano |
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Method and apparatus for managing the power consumption of a data processing system |
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Delay budget allocation with path trimming |
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2010-03-16 |
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System and method for reducing store latency in symmetrical multiprocessor systems |
Jonathan James DeMent, Roy Moonseuk Kim, Kevin C. Stelzer, Thuong Quang Truong |
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Livelock resolution method |
Charles Ray Johns, David J. Krolak, Peichun Peter Liu |
2009-03-03 |
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Method and apparatus for managing the power consumption of a data processing system |
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Fixed snoop response time for source-clocked multiprocessor busses |
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Method of analyzing and filtering timing runs using common timing characteristics |
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Dual-L2 processor subsystem architecture for networking system |
— |
2004-06-15 |
| 4761730 |
Computer memory apparatus |
Edwin P. Fisher |
1988-08-02 |
| 4739473 |
Computer memory apparatus |
Edwin P. Fisher |
1988-04-19 |
