TU

Taku Uchino

KT Kabushiki Kaisha Toshiba: 6 patents #4,898 of 21,451Top 25%
IBM: 2 patents #32,839 of 70,183Top 50%
📍 Yokohama, CA: #241 of 287 inventorsTop 85%
Overall (All Time): #859,194 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
8370783 Systems and methods for probabilistic interconnect planning Alvan W. Ng 2013-02-05
7681158 Delay budget allocation with path trimming Alvan W. Ng 2010-03-16
7076405 Method for estimating power consumption and noise levels of an integrated circuit, and computer-readable recording medium storing a program for estimating power consumption and noise levels of an integrated circuit 2006-07-11
6272663 System and method for reducing undesired radiation generated by LSI 2001-08-07
5966523 Method of estimating power consumption of semiconductor integrated circuit 1999-10-12
5847966 Power estimation method for an integrated circuit using probability calculations Takashi Mitsuhashi 1998-12-08