RK

Rajesh Katkar

IN Invensas: 110 patents #3 of 142Top 3%
AT Adeia Semiconductor Bonding Technologies: 57 patents #3 of 46Top 7%
IT Invensas Bonding Technologies: 27 patents #2 of 21Top 10%
XC Xcelsis: 6 patents #7 of 19Top 40%
AS Adeia Semiconductor: 3 patents #6 of 14Top 45%
TE Tessera: 2 patents #162 of 271Top 60%
NI Nice: 1 patents #150 of 298Top 55%
📍 San Jose, CA: #50 of 32,062 inventorsTop 1%
🗺 California: #519 of 386,348 inventorsTop 1%
Overall (All Time): #3,126 of 4,157,543Top 1%
206
Patents All Time

Issued Patents All Time

Showing 126–150 of 206 patents

Patent #TitleCo-InventorsDate
10181457 Microelectronic package for wafer-level chip scale packaging with fan-out Ashok S. Prabhu 2019-01-15
10163833 Multichip modules and methods of fabrication Liang Wang, Hong Shen 2018-12-25
10159148 Porous alumina templates for electronic packages Cyprian Emeka Uzoh, Belgacem Haba, Ilyas Mohammed 2018-12-18
10147548 Capacitors using porous alumina structures Cyprian Emeka Uzoh 2018-12-04
10103121 Tall and fine pitch interconnects Cyprian Emeka Uzoh 2018-10-16
10090231 Conductive connections, structures with such connections, and methods of manufacture Cyprian Emeka Uzoh 2018-10-02
10049998 Conductive connections, structures with such connections, and methods of manufacture Cyprian Emeka Uzoh 2018-08-14
10043779 Packaged microelectronic device for a package-on-package device Ashok S. Prabhu 2018-08-07
10032647 Low CTE component with wire bond interconnects Cyprian Emeka Uzoh 2018-07-24
10026717 Multiple bond via arrays of different wire heights on a same substrate Cyprian Emeka Uzoh 2018-07-17
10014243 Interconnection substrates for interconnection between circuit modules, and methods of manufacture Hong Shen, Liang Wang, Gabriel Z. Guevara, Cyprian Emeka Uzoh, Laura Wills Mirkarimi 2018-07-03
10008469 Wafer-level packaging using wire bond wires in place of a redistribution layer Tu Tam Vu, Bongsub Lee, Kyong-Mo Bang, Xuan Li, Long Huynh +4 more 2018-06-26
10008534 Microelectronic package with horizontal and vertical interconnections Cyprian Emeka Uzoh 2018-06-26
10002844 Bonded structures Liang Wang, Javier A. Delacruz, Arkalgud R. Sitaram 2018-06-19
9947641 Wire bond support structure and microelectronic package including wire bonds therefrom Reynaldo Co, Wael Zohni, Rizza Lee Saga Cizek 2018-04-17
9911718 ‘RDL-First’ packaged microelectronic device for a package-on-package device Ashok S. Prabhu 2018-03-06
9899442 Image sensor device 2018-02-20
9888584 Contact structures with porous networks for solder connections, and methods of fabricating same Liang Wang, Hong Shen, Cyprian Emeka Uzoh 2018-02-06
9887166 Integrated circuit assemblies with reinforcement frames, and methods of manufacture Laura Wills Mirkarimi, Arkalgud R. Sitaram, Charles G. Woychik 2018-02-06
9871019 Flipped die stack assemblies with leadframe interconnects Ashok S. Prabhu, Liang Wang, Cyprian Emeka Uzoh 2018-01-16
9865675 Making multilayer 3D capacitors using arrays of upstanding rods or ridges Liang Wang, Hong Shen, Cyprian Emeka Uzoh 2018-01-09
9865548 Polymer member based interconnect Cyprian Emeka Uzoh, Charles G. Woychik, Guilian Gao, Arkalgud R. Sitaram 2018-01-09
9859257 Flipped die stacks with multiple rows of leadframe interconnects Javier A. Delacruz, Belgacem Haba, Tu Tam Vu 2018-01-02
9852969 Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects Cyprian Emeka Uzoh 2017-12-26
9847238 Fan-out wafer-level packaging using metal foil lamination Xuan Li, Long Huynh, Laura Wills Mirkarimi, Bongsub Lee, Gabriel Z. Guevara +3 more 2017-12-19