Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9971705 | Virtual memory address range register | Gur Hildesheim, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis X. McKeen +3 more | 2018-05-15 |
| 9925492 | Remote transactional memory | Liran Liss, Ariel Shachar, Noam Bloch, Michael Kagan | 2018-03-27 |
| 9785462 | Registering a user-handler in hardware for transactional memory event handling | Gad Sheaffer, Vadim Bassin | 2017-10-10 |
| 9753889 | Gather using index array and finite state machine | Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Igor Yanover +1 more | 2017-09-05 |
| 9734079 | Hybrid exclusive multi-level memory architecture with memory management | Dannie Gerrit Feekes, Blaise Fanning, Joydeep Ray, Julius Mandelblat, Ariel Berkovits +3 more | 2017-08-15 |
| 9727503 | Storage system and server | Michael Kagan, Noam Bloch, Yaron Haviv, Idan Burstein | 2017-08-08 |
| 9720843 | Access type protection of memory reserved for use by processor logic | Gur Hildesheim, Ittai Anati, Gideon Gerzon, Hisham Shafi, Alex Berenzon +2 more | 2017-08-01 |
| 9699110 | Accelerating and offloading lock access over a network | Dror Goldenberg, Liran Liss | 2017-07-04 |
| 9696942 | Accessing remote storage devices using a local bus protocol | Michael Kagan, Noam Bloch, Yaron Haviv, Idan Burstein | 2017-07-04 |
| 9678818 | Direct IO access from a CPU's instruction stream | Noam Bloch, Richard Graham, Ofer Hayut, Michael Kagan, Liran Liss | 2017-06-13 |
| 9672019 | Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads | David J. Sager, Ruchira Sasanka, Ron Gabor, Joseph Nuzman, Leeor Peled +10 more | 2017-06-06 |
| 9648081 | Network-attached memory | Shachar Raindel, Michael Kagan | 2017-05-09 |
| 9632901 | Page resolution status reporting | Shachar Raindel, Noam Bloch, Liran Liss | 2017-04-25 |
| 9626333 | Scatter using index array and finite state machine | Zeev Sperber, Robert Valentine, Stanislav Shwartsman, Gal Ofir, Igor Yanover +2 more | 2017-04-18 |
| 9524240 | Obscuring memory access patterns in conjunction with deadlock detection or avoidance | Shay Gueron, Gad Sheaffer | 2016-12-20 |
| 9424198 | Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory | Zvika Greenfield | 2016-08-23 |
| 9411728 | Methods and apparatus for efficient communication between caches in hierarchical caching design | Ron Shalev, Yiftach Gilad, Igor Yanover, Stanislav Shwartsman, Raanan Sade | 2016-08-09 |
| 9405545 | Method and apparatus for cutting senior store latency using store prefetching | Stanislav Shwartsman, Melih Ozgul, Sebastien Hily, Raanan Sade, Ron Shalev | 2016-08-02 |
| 9348766 | Balanced P-LRU tree for a “multiple of 3” number of ways cache | Adi Basel, Gur Hildesheim, Robert S. Chappell, Ho-Seop Kim, Rohit Bhatia | 2016-05-24 |
| 9286235 | Virtual memory address range register | Gur Hildesheim, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis X. McKeen +3 more | 2016-03-15 |
| 9268697 | Snoop filter having centralized translation circuitry and shadow tag array | Ilan Pardo, Niranjan L. Cooray, Stanislav Shwartsman | 2016-02-23 |
| 9183161 | Apparatus and method for page walk extension for enhanced security checks | Gur Hildesheim, Ittai Anati, Hisham Shafi, Gideon Gerzon, Uday Savagaonkar +4 more | 2015-11-10 |
| 9027009 | Protecting the integrity of binary translated code | Lihu Rappoport, Joseph Nuzman | 2015-05-05 |
| 8972697 | Gather using index array and finite state machine | Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Igor Yanover +1 more | 2015-03-03 |
| 8914617 | Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register | David J. Sager, Zeev Sperber, Evgeni Krimer, Ori Lempel, Stanislav Shwartsman +2 more | 2014-12-16 |