Issued Patents All Time
Showing 51–67 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8806101 | Metaphysical address space for holding lossy metadata in hardware | Gad Sheaffer, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis | 2014-08-12 |
| 8799582 | Extending cache coherency protocols to support locally buffered data | Gad Sheaffer, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis | 2014-08-05 |
| 8769212 | Memory model for hardware attributes within a transactional memory system | Gad Sheaffer, Vadim Bassin, Ehud Cohen, Oleg Margulis | 2014-07-01 |
| 8688917 | Read and write monitoring attributes in transactional memory (TM) systems | Gad Sheaffer, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis | 2014-04-01 |
| 8688962 | Gather cache architecture | Robert Valentine | 2014-04-01 |
| 8627014 | Memory model for hardware attributes within a transactional memory system | Gad Sheaffer, Vadim Bassin, Ehud Cohen, Oleg Margulis | 2014-01-07 |
| 8627017 | Read and write monitoring attributes in transactional memory (TM) systems | Gad Sheaffer, Vadim Bassin, Raanan Sade, Ehud Cohen, Oleg Margulis | 2014-01-07 |
| 8516201 | Protecting private data from cache attacks | Shay Gueron, Gad Sheaffer | 2013-08-20 |
| 8516577 | Regulating atomic memory operations to prevent denial of service attack | Michael S. Bair, David William Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong +4 more | 2013-08-20 |
| 8407425 | Obscuring memory access patterns in conjunction with deadlock detection or avoidance | Shay Gueron, Gad Sheaffer | 2013-03-26 |
| 8370577 | Metaphysically addressed cache metadata | Gad Sheaffer, David Callahan, Jan Gray, Ali-Reza Adl-Tabatabai | 2013-02-05 |
| 8347035 | Posting weakly ordered transactions | Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Zeev Offen +2 more | 2013-01-01 |
| 8341356 | Protected cache architecture and secure programming paradigm to protect applications | Shay Gueron, Gad Sheaffer | 2012-12-25 |
| 8209689 | Live lock free priority scheme for memory transactions in transactional memory | Shay Gueron, Gad Sheaffer | 2012-06-26 |
| 7975129 | Selective hardware lock disabling | Gad Sheaffer, Doron Orenstlen | 2011-07-05 |
| 7958320 | Protected cache architecture and secure programming paradigm to protect applications | Shay Gueron, Gad Sheaffer | 2011-06-07 |
| 7613908 | Selective hardware lock disabling | Gad Sheaffer, Doron Orenstien | 2009-11-03 |