Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10713177 | Defining virtualized page attributes based on guest page attributes | Gilbert Neiger, Baiju V. Patel, Ron Rais, Andrew V. Anderson, Jason W. Brandt +6 more | 2020-07-14 |
| 10114768 | Enhance memory access permission based on per-page current privilege level | Gilbert Neiger, Baiju V. Patel, Ron Rais | 2018-10-30 |
| 9971705 | Virtual memory address range register | Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis X. McKeen +3 more | 2018-05-15 |
| 9720843 | Access type protection of memory reserved for use by processor logic | Shlomo Raikin, Ittai Anati, Gideon Gerzon, Hisham Shafi, Alex Berenzon +2 more | 2017-08-01 |
| 9348766 | Balanced P-LRU tree for a “multiple of 3” number of ways cache | Adi Basel, Shlomo Raikin, Robert S. Chappell, Ho-Seop Kim, Rohit Bhatia | 2016-05-24 |
| 9286235 | Virtual memory address range register | Shlomo Raikin, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis X. McKeen +3 more | 2016-03-15 |
| 9183161 | Apparatus and method for page walk extension for enhanced security checks | Ittai Anati, Hisham Shafi, Shlomo Raikin, Gideon Gerzon, Uday Savagaonkar +4 more | 2015-11-10 |
| 9069690 | Concurrent page table walker control for TLB miss handling | Chang Kian Tan, Robert S. Chappell, Rohit Bhatia | 2015-06-30 |