Issued Patents All Time
Showing 76–100 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7716623 | Programmable logic device architectures and methods for implementing logic in those architectures | Tim Vanderhoek, Vaughn Betz, David Cashman, David Lewis | 2010-05-11 |
| 7705628 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Andy L. Lee, Gregg William Baeckler, Jinyong Yuan, Keith Duwel | 2010-04-27 |
| 7689955 | Register retiming technique | Babette van Antwerpen, Gregg William Baeckler, Richard Yuan | 2010-03-30 |
| 7675319 | Programmable logic device having complex logic blocks with improved logic cell functionality | — | 2010-03-09 |
| 7671625 | Omnibus logic element | James Schleicher, Richard Yuan, Bruce B. Pedersen, Sinan Kaptanoglu, Gregg William Baeckler +4 more | 2010-03-02 |
| 7619443 | Programmable logic device architectures and methods for implementing logic in those architectures | Tim Vanderhoek, Vaughn Betz, David Cashman, David Lewis | 2009-11-17 |
| 7605603 | User-accessible freeze-logic for dynamic power reduction and associated methods | Andy L. Lee | 2009-10-20 |
| 7607118 | Techniques for using edge masks to perform timing analysis | — | 2009-10-20 |
| 7579866 | Programmable logic device with configurable override of region-wide signals | David Cashman, Jinyoung Yuan, Kimberly Bozman | 2009-08-25 |
| 7577929 | Early timing estimation of timing statistical properties of placement | David Karchmer | 2009-08-18 |
| 7545196 | Clock distribution for specialized processing block in programmable logic device | Kumara Tharmalingam, Yi-Wen Lin, David Neto | 2009-06-09 |
| 7509618 | Method and apparatus for facilitating an adaptive electronic design automation tool | Yean-Yow Hwang, David W. Mendel | 2009-03-24 |
| 7492188 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2009-02-17 |
| 7469394 | Timing variation aware compilation | Yan Lin | 2008-12-23 |
| 7420390 | Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size | James Schleicher | 2008-09-02 |
| 7394287 | Programmable logic device having complex logic blocks with improved logic cell functionality | — | 2008-07-01 |
| 7373631 | Methods of producing application-specific integrated circuit equivalents of programmable logic | Jinyong Yuan, Gregg William Baeckler, James Schleicher | 2008-05-13 |
| 7368944 | Organizations of logic modules in programmable logic devices | Bruce B. Pedersen, Sinan Kaptanoglu, David Lewis, Tim Vanderhoek | 2008-05-06 |
| 7368942 | Dedicated resource interconnects | Bruce B. Pedersen, James Schleicher | 2008-05-06 |
| 7355442 | Dedicated crossbar and barrel shifter block on programmable logic resources | Sinan Kaptanoglu | 2008-04-08 |
| 7350176 | Techniques for mapping to a shared lookup table mask | Gregg William Baeckler | 2008-03-25 |
| 7337100 | Physical resynthesis of a logic design | Joachim Pistorius, Babette van Antwerpen, Gregg William Baeckler, Richard Yuan, Yean-Yow Hwang | 2008-02-26 |
| 7330052 | Area efficient fractureable logic elements | Sinan Kaptanoglu, Bruce B. Pedersen, James Schleicher, Jinyong Yuan, David Lewis | 2008-02-12 |
| 7312633 | Programmable routing structures providing shorter timing delays for input/output signals | David Lewis | 2007-12-25 |
| 7248072 | Swap MUX to relieve logic device input line stress | Vaughn Betz | 2007-07-24 |