Issued Patents All Time
Showing 101–113 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7176718 | Organizations of logic modules in programmable logic devices | Bruce B. Pedersen, Sinan Kaptanoglu, David Lewis, Tim Vanderhoek | 2007-02-13 |
| 7135888 | Programmable routing structures providing shorter timing delays for input/output signals | David Lewis | 2006-11-14 |
| 7133819 | Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices | — | 2006-11-07 |
| 7120883 | Register retiming technique | Babette van Antwerpen, Gregg William Baeckler, Richard Yuan | 2006-10-10 |
| 7093219 | Techniques for using edge masks to perform timing analysis | — | 2006-08-15 |
| 7042248 | Dedicated crossbar and barrel shifter block on programmable logic resources | Sinan Kaptanoglu | 2006-05-09 |
| 7010777 | Shared lookup table enhancements for the efficient implementation of barrel shifters | Andy L. Lee, Rahul Saini | 2006-03-07 |
| 6989689 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2006-01-24 |
| 6977520 | Time-multiplexed routing in a programmable logic device architecture | Richard G. Cliff | 2005-12-20 |
| 6894533 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2005-05-17 |
| 6747480 | Programmable logic devices with bidirect ional cascades | Sinan Kaptanoglu, James Schleicher | 2004-06-08 |
| 6429681 | Programmable logic device routing architecture to facilitate register re-timing | — | 2002-08-06 |
| 6407576 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2002-06-18 |