Issued Patents All Time
Showing 51–75 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8542032 | Integrated circuits with interconnect selection circuitry | Irfan Rahim | 2013-09-24 |
| 8521801 | Configurable hybrid adder circuitry | Erhard Joachim Pistorius | 2013-08-27 |
| 8519740 | Integrated circuits with shared interconnect buses | David Lewis | 2013-08-27 |
| 8402408 | Register retiming technique | Babette van Antwerpen, Gregg William Baeckler, Richard Yuan | 2013-03-19 |
| 8381142 | Using a timing exception to postpone retiming | — | 2013-02-19 |
| 8314636 | Field programmable gate array with integrated application specific integrated circuit fabric | James Schleicher, Daniel R. Mansur | 2012-11-20 |
| 8185854 | Method and apparatus for performing parallel slack computation within a shared netlist region | Jason Govig | 2012-05-22 |
| 8166427 | Tracing and reporting registers removed during synthesis | Swatiben Ruturaj Pathak, Babette van Antwerpen, Andrew Leaver | 2012-04-24 |
| 8112728 | Early timing estimation of timing statistical properties of placement | David Karchmer | 2012-02-07 |
| 8108812 | Register retiming technique | Babette van Antwerpen, Gregg William Baeckler, Richard Yuan | 2012-01-31 |
| 8082526 | Dedicated crossbar and barrel shifter block on programmable logic resources | Sinan Kaptanoglu | 2011-12-20 |
| 8072238 | Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions | — | 2011-12-06 |
| 8020027 | Timing control in a specialized processing block | — | 2011-09-13 |
| 8001499 | Circuit type pragma for computer aided design tools | Greg William Baeckler, David W. Mendel | 2011-08-16 |
| 7902864 | Heterogeneous labs | Keith Duwel, Gregg William Baeckler | 2011-03-08 |
| 7890910 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Gregg William Baeckler, Jinyong Yuan, Chris Wysocki, Pouyan Djahani | 2011-02-15 |
| 7839167 | Interconnection and input/output resources for programmable logic integrated circuit devices | Tony Ngai, Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang +6 more | 2010-11-23 |
| 7839165 | User-accessible freeze-logic for dynamic power reduction and associated methods | Andy L. Lee | 2010-11-23 |
| 7827433 | Time-multiplexed routing for reducing pipelining registers | — | 2010-11-02 |
| 7818705 | Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew | David Lewis | 2010-10-19 |
| 7812635 | Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions | — | 2010-10-12 |
| 7804325 | Dedicated function block interfacing with general purpose function blocks on integrated circuits | Erhard Joachim Pistorius | 2010-09-28 |
| 7784008 | Performance visualization system | David Karchmer, Zhiru Zhang | 2010-08-24 |
| 7733124 | Method and apparatus for PLD having shared storage elements | Keith Duwel | 2010-06-08 |
| 7724032 | Field programmable gate array with integrated application specific integrated circuit fabric | James Schleicher, Daniel R. Mansur | 2010-05-25 |