Issued Patents All Time
Showing 26–50 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9507883 | Method and apparatus for implementing a system-level design tool for design planning and architecture exploration | Herman Schmit | 2016-11-29 |
| 9478272 | Configurable storage blocks with embedded first-in first-out and last-in first-out circuitry | Richard A. Grenier | 2016-10-25 |
| 9479456 | Programmable logic device with integrated network-on-chip | Herman Schmit, Dana How | 2016-10-25 |
| 9471537 | Hybrid programmable many-core device with on-chip interconnect | Anargyros Krikelis | 2016-10-18 |
| 9471388 | Mapping network applications to a hybrid programmable many-core device | Anargyros Krikelis | 2016-10-18 |
| 9450609 | Methods and apparatus for embedding an error correction code in memory cells | Herman Schmit | 2016-09-20 |
| 9294092 | Error resilient packaged components | — | 2016-03-22 |
| 9292474 | Configurable hybrid adder circuitry | Erhard Joachim Pistorius | 2016-03-22 |
| 9276582 | Method and circuit for scalable cross point switching using 3-D die stacking | Jeffrey Erik Schulz | 2016-03-01 |
| 9251300 | Methods and tools for designing integrated circuits with auto-pipelining capabilities | Chuck Rumbolt, Jeffrey R. Fox, Herman Henry Schmidt | 2016-02-02 |
| 9230048 | Integrated circuits with interconnect selection circuitry | Irfan Rahim | 2016-01-05 |
| 9178513 | Memory blocks with shared address bus circuitry | David Lewis | 2015-11-03 |
| 9172378 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Gregg William Baeckler, Jinyong Yuan, Chris Wysocki, Pouyan Djahani | 2015-10-27 |
| 9166599 | Methods and apparatus for building bus interconnection networks using programmable interconnection resources | — | 2015-10-20 |
| 9165931 | Apparatus for field-programmable gate array with configurable architecture and associated methods | Herman Schmit, David Lewis, Dana How, Andy L. Lee | 2015-10-20 |
| 9106229 | Programmable interposer circuitry | Richard A. Grenier | 2015-08-11 |
| 9077338 | Method and circuit for scalable cross point switching using 3-D die stacking | Jeffrey Erik Schulz | 2015-07-07 |
| 9053274 | Register retiming technique | Babette van Antwerpen, Gregg William Baeckler, Jinyong Yuan | 2015-06-09 |
| 8997029 | Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew | David Lewis | 2015-03-31 |
| 8860458 | Integrated circuits with logic regions having input and output bypass paths for accessing registers | — | 2014-10-14 |
| 8854080 | Integrated circuits with interconnect selection circuitry | Irfan Rahim | 2014-10-07 |
| 8806399 | Register retiming technique | Babette van Antwerpen, Gregg William Baeckler, Jinyong Yuan | 2014-08-12 |
| 8704548 | Methods and apparatus for building bus interconnection networks using programmable interconnection resources | — | 2014-04-22 |
| 8640067 | Method and apparatus for implementing a field programmable gate array clock skew | David Lewis | 2014-01-28 |
| 8601424 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Gregg William Baeckler, Jinyong Yuan, Chris Wysocki, Pouyan Djahani | 2013-12-03 |