Issued Patents All Time
Showing 151–175 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10553268 | Methods and apparatus to perform complex number generation and operation on a chip | Sasikanth Manipatruni, Dmitri E. Nikonov | 2020-02-04 |
| 10535770 | Scaled TFET transistor formed using nanowire with surface termination | Uygar E. Avci, Rafael Rios, Kelin J. Kuhn, Justin R. Weber | 2020-01-14 |
| 10522683 | Transistors with ballistic or quasi-ballistic carrier behavior and low resistance in source and drain nodes | Raseong Kim, Uygar E. Avci | 2019-12-31 |
| 10483026 | Metallic spin super lattice for logic and memory devices | Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov | 2019-11-19 |
| 10483455 | Magnetic element for memory and logic | Dmitri E. Nikonov | 2019-11-19 |
| 10457548 | Integrating MEMS structures with interconnects and vias | Kevin Lin, Chytra Pawashe, Raseong Kim, Kanwal Jit Singh, Robert L. Bristol | 2019-10-29 |
| 10439599 | Non-boolean associative processor degree of match and winner take all circuits | Dmitri E. Nikonov | 2019-10-08 |
| 10416217 | On-chip test circuit for magnetic random access memory (MRAM) | Sasikanth Manipatruni, Chia-Ching Lin, Yih Wang | 2019-09-17 |
| 10355005 | Semi-volatile embedded memory with between-fin floating-gate device and method | Uygar E. Avci, Daniel H. Morris, Stephen M. Ramey | 2019-07-16 |
| 10347830 | Non-volatile register file including memory cells having conductive oxide memory element | Sasikanth Manipatruni, Elijah Ilya Karpov, Brian S. Doyle, Dmitri E. Nikonov | 2019-07-09 |
| 10331582 | Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time | Ishwar Bhati, Huichu Liu, Jayesh Gaur, Kunal Kishore Korgaonkar, Sasikanth Manipatruni +3 more | 2019-06-25 |
| 10333523 | Exclusive-OR logic device with spin orbit torque effect | Sasikanth Manipatruni, Dmitri E. Nikonov | 2019-06-25 |
| 10320404 | Coupled spin hall nano oscillators with tunable strength | Sasikanth Manipatruni, George I. Bourianoff, Dmitri E. Nikonov | 2019-06-11 |
| 10263036 | Strain assisted spin torque switching spin transfer torque memory | Sasikanth Manipatruni, Dmitri E. Nikonov, Asif Khan, Raseong Kim, Tahir Ghani | 2019-04-16 |
| 10261923 | Configurable interconnect apparatus and method | Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Tanay Karnik, Huichu Liu | 2019-04-16 |
| 10236345 | Field effect transistor having a Fermi filter between a source and source contact thereof | Uygar E. Avci | 2019-03-19 |
| 10170185 | Hybrid memory and MTJ based MRAM bit-cell and array | Sasikanth Manipatruni | 2019-01-01 |
| 10128356 | P-tunneling field effect transistor device with pocket | Uygar E. Avci, Roza Kotlyar | 2018-11-13 |
| 10062731 | Spin-orbit logic with charge interconnects and magnetoelectric nodes | Sasikanth Manipatruni, Dmitri E. Nikonov | 2018-08-28 |
| 10043971 | Non-volatile register file including memory cells having conductive oxide memory element | Sasikanth Manipatruni, Elijah Ilya Karpov, Brian S. Doyle, Dmitri E. Nikonov | 2018-08-07 |
| 9997227 | Non-volatile ferroelectric logic with granular power-gating | Daniel H. Morris, Uygar E. Avci | 2018-06-12 |
| 9985611 | Tunnel field-effect transistor (TFET) based high-density and low-power sequential | Daniel H. Morris, Uygar E. Avci | 2018-05-29 |
| 9947805 | Nanowire-based mechanical switching device | Chytra Pawashe, Kevin Lin, Anurag Chaudhry, Raseong Kim, Seiyon Kim +3 more | 2018-04-17 |
| 9927211 | Cloaking system with waveguides | Johanna M. Swan, Robert L. Sankman, Marko Radosavljevic | 2018-03-27 |
| 9911835 | Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs | Roza Kotlyar, Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci +4 more | 2018-03-06 |