Issued Patents All Time
Showing 26–50 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710391 | Methods and apparatuses for efficient load processing using buffers | Wei Liu, Youfeng Wu, Christopher B. Wilkerson | 2017-07-18 |
| 9626321 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2017-04-18 |
| 9311085 | Compiler assisted low power and high performance load handling based on load types | Tingting Sha, Chris Wilkerson, Alaa R. Alameldeen | 2016-04-12 |
| 9170946 | Directory cache supporting non-atomic input/output operations | James Vash, Eric Andrew Gouldey, Ganesh Kumar, David Bubien, Manoj K. Arora +3 more | 2015-10-27 |
| 9037903 | Apparatus and method for partial memory mirroring | Ganesh Kumar, Robert C. Swanson, David Bubien | 2015-05-19 |
| 8885673 | Interleaving data packets in a packet-based communication system | Aaron T. Spink | 2014-11-11 |
| 8789031 | Software constructed strands for execution on a multi-core architecture | Wei Liu, Lixin Su, Youfeng Wu | 2014-07-22 |
| 8631210 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Adrian C. Moga, Malcolm Mandviwalla, Vedaraman Geetha | 2014-01-14 |
| 8615647 | Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state | Eric Sprangle, Doug Carmean, Rajesh Kumar | 2013-12-24 |
| 8452946 | Methods and apparatuses for efficient load processing using buffers | Wei Liu, Youfeng Wu, Christopher B. Wilkerson | 2013-05-28 |
| 8392665 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Adrian C. Moga, Malcolm Mandviwalla, Vedaraman Geetha | 2013-03-05 |
| 8325768 | Interleaving data packets in a packet-based communication system | Aaron T. Spink | 2012-12-04 |
| 8171095 | Speculative distributed conflict resolution for a cache coherency protocol | James R. Goodman, Robert Beers, Rajnish Ghughal | 2012-05-01 |
| 8151096 | Method to improve branch prediction latency | Hongliang Gao | 2012-04-03 |
| 8099587 | Compressing and accessing a microcode ROM | Youfeng Wu, Sangwook Kim, Mauricio Breternitz | 2012-01-17 |
| 7996572 | Multi-node chipset lock flow with peer-to-peer non-posted I/O requests | Robert G. Blankenship, Robert Greiner, Kenneth C. Creta, Buderya Acharya | 2011-08-09 |
| 7958336 | System and method for reservation station load dependency matrix | Sagi Lahav, Guy Patkin, Zeev Sperber, Shih-Lien Linus Lu, Srikanth Srinivasan | 2011-06-07 |
| 7921251 | Globally unique transaction identifiers | Aaron T. Spink, Robert G. Blankenship | 2011-04-05 |
| 7917646 | Speculative distributed conflict resolution for a cache coherency protocol | James R. Goodman, Robert Beers, Rajnish Ghughal | 2011-03-29 |
| 7783809 | Virtualization of pin functionality in a point-to-point interface | Keshavan Tiruvallur, David I. Poisner, Frank Binns, David L. Hill, Robert Greiner +1 more | 2010-08-24 |
| 7721050 | Re-snoop for conflict resolution in a cache coherency protocol | Robert Beers | 2010-05-18 |
| 7716409 | Globally unique transaction identifiers | Aaron T. Spink, Robert G. Blankenship | 2010-05-11 |
| 7643477 | Buffering data packets according to multiple flow control schemes | Aaron T. Spink | 2010-01-05 |
| 7512750 | Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information | Chris J. Newburn, Ram Huggahalli, Ali-Reza Adl-Tabatabai, Anwar Ghuloum | 2009-03-31 |
| 7506108 | Requester-generated forward for late conflicts in a cache coherency protocol | Robert Beers | 2009-03-17 |