Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7457924 | Hierarchical directories for cache coherency in a multiprocessor system | James R. Goodman | 2008-11-25 |
| 7434006 | Non-speculative distributed conflict resolution for a cache coherency protocol | Robert Beers, James R. Goodman | 2008-10-07 |
| 7360033 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system | James R. Goodman | 2008-04-15 |
| 7350016 | High speed DRAM cache architecture | Kuljit S. Bains, John B. Halbert | 2008-03-25 |
| 7269698 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system | James R. Goodman | 2007-09-11 |
| 7257693 | Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system | Chris J. Newburn, Ram Huggahalli, Ali-Reza Adl-Tabatabai, Anwar Ghuloum | 2007-08-14 |
| 7203825 | Sharing information to reduce redundancy in hybrid branch prediction | Stephan Jourdan | 2007-04-10 |
| 7130969 | Hierarchical directories for cache coherency in a multiprocessor system | James R. Goodman | 2006-10-31 |
| 7111128 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system | James R. Goodman | 2006-09-19 |
| 7095342 | Compressing microcode | Mauricio Breternitz, Youfeng Wu, Sangwook Kim | 2006-08-22 |
| 7080209 | Method and apparatus for processing a load-lock instruction using a relaxed lock protocol | Doug Carmean | 2006-07-18 |
| 7054999 | High speed DRAM cache architecture | Kuljit S. Bains, John B. Halbert | 2006-05-30 |
| 6990551 | System and method for employing a process identifier to minimize aliasing in a linear-addressed cache | Stephan Jourdan, Per Hammarlund | 2006-01-24 |
| 6961823 | Stream-down prefetching cache | Zohar Bogin | 2005-11-01 |
| 6954829 | Non-speculative distributed conflict resolution for a cache coherency protocol | Robert Beers, James R. Goodman | 2005-10-11 |
| 6954822 | Techniques to map cache data to memory arrays | Kuljit S. Bains, John B. Halbert | 2005-10-11 |
| 6922745 | Method and apparatus for handling locks | Harish Kumar, Aravindh Baktha, Mike Upton, KS Venkatraman, Zhongying Zhang | 2005-07-26 |
| 6922756 | Forward state for use in cache coherency in a multiprocessor system | James R. Goodman | 2005-07-26 |
| 6798364 | Method and apparatus for variable length coding | Yen-Kuang Chen, Matthew Holliman, Per Hammarlund, Thomas R. Huff, William W. Macy | 2004-09-28 |
| 6675282 | System and method for employing a global bit for page sharing in a linear-addressed cache | Stephan Jourdan, Deborrah Marr, Per Hammarlund | 2004-01-06 |
| 6643743 | Stream-down prefetching cache | Zohar Bogin | 2003-11-04 |
| 6594730 | Prefetch system for memory controller | Andrew V. Anderson | 2003-07-15 |
| 6560690 | System and method for employing a global bit for page sharing in a linear-addressed cache | Stephan Jourdan, Deborrah Marr, Per Hammarlund | 2003-05-06 |
| 6078992 | Dirty line cache | — | 2000-06-20 |