Issued Patents All Time
Showing 76–100 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6105111 | Method and apparatus for providing a cache management technique | Per Hammarlund | 2000-08-15 |
| 6101597 | Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor | Robert P. Colwell, Michael A. Fetterman, Robert W. Martell, David B. Papworth | 2000-08-08 |
| 6079014 | Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state | David B. Papworth, Michael A. Fetterman, Andrew F. Glew, Robert P. Colwell | 2000-06-20 |
| 6047369 | Flag renaming and flag masks within register alias table | Robert P. Colwell, Andrew F. Glew, Atiq Bajwa, Michael A. Fetterman | 2000-04-04 |
| 6018786 | Trace based instruction caching | Robert F. Krick, Michael D. Upton, David J. Sager, Chan Woo Lee | 2000-01-25 |
| 5987600 | Exception handling in a processor that performs speculative out-of-order instruction execution | David B. Papworth, Michael A. Fetterman, Robert P. Colwell, Andrew F. Glew | 1999-11-16 |
| 5974523 | Mechanism for efficiently overlapping multiple operand types in a microprocessor | Andrew F. Glew, Darrell D. Boggs, Michael A. Fetterman, Robert P. Colwell, David B. Papworth | 1999-10-26 |
| 5918046 | Method and apparatus for a branch instruction pointer table | Bradley D. Hoyt, David B. Papworth, Subramanian Natarajan, Reynold V. D'Sa | 1999-06-29 |
| 5913050 | Method and apparatus for providing address-size backward compatibility in a processor using segmented memory | Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, David B. Papworth | 1999-06-15 |
| 5903751 | Method and apparatus for implementing a branch target buffer in CISC processor | Bradley D. Hoyt, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1999-05-11 |
| 5881262 | Method and apparatus for blocking execution of and storing load operations during their execution | Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland | 1999-03-09 |
| 5870599 | Computer system employing streaming buffer for instruction preetching | Ashwani K. Gupta, Sunil Shenoy | 1999-02-09 |
| 5860154 | Method and apparatus for calculating effective memory addresses | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland +1 more | 1999-01-12 |
| 5854914 | Mechanism to improved execution of misaligned loads | Milind A. Bodas, Andrew F. Glew | 1998-12-29 |
| 5845100 | Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length | Ashwani K. Gupta, Chan Woo Lee | 1998-12-01 |
| 5842036 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz | 1998-11-24 |
| 5828868 | Processor having execution core sections operating at different clock rates | David J. Sager, Thomas D. Fletcher, Michael D. Upton | 1998-10-27 |
| 5826109 | Method and apparatus for performing multiple load operations to the same memory location in a computer system | Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland +2 more | 1998-10-20 |
| 5826094 | Register alias table update to indicate architecturally visible state | Robert P. Colwell, David B. Papworth, Michael A. Fetterman, Andrew F. Glew | 1998-10-20 |
| 5812839 | Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit | Bradley D. Hoyt, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1998-09-22 |
| 5809325 | Circuit and method for scheduling instructions by predicting future availability of resources required for execution | Robert W. Martell, Michael A. Fetterman, David B. Papworth, James L. Schwartz | 1998-09-15 |
| 5809271 | Method and apparatus for changing flow of control in a processor | Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, David B. Papworth | 1998-09-15 |
| 5778245 | Method and apparatus for dynamic allocation of multiple buffers in a processor | David B. Papworth, Andrew F. Glew, Robert P. Colwell, Michael A. Fetterman, Shantanu Gupta +1 more | 1998-07-07 |
| 5778407 | Methods and apparatus for determining operating characteristics of a memory element based on its physical location | Andrew F. Glew, David B. Papworth, Michael A. Fetterman, Robert P. Colwell, Frederick J. Pollack | 1998-07-07 |
| 5768576 | Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor | Bradley D. Hoyt, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1998-06-16 |