Issued Patents All Time
Showing 101–125 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5751996 | Method and apparatus for processing memory-type information within a microprocessor | Andrew F. Glew | 1998-05-12 |
| 5751986 | Computer system with self-consistent ordering mechanism | Michael A. Fetterman, David B. Papworth, Andrew F. Glew, Robert P. Colwell | 1998-05-12 |
| 5751983 | Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations | Jeffrey M. Abramson, David B. Papworth, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld +1 more | 1998-05-12 |
| 5748937 | Computer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructions | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland | 1998-05-05 |
| 5729728 | Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor | Robert P. Colwell, Atiq Bajwa, Michael A. Fetterman, Andrew F. Glew, David B. Papworth | 1998-03-17 |
| 5724536 | Method and apparatus for blocking execution of and storing load operations during their execution | Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland | 1998-03-03 |
| 5721855 | Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer | David B. Papworth, Andrew F. Glew, Michael A. Fetterman, Robert P. Colwell | 1998-02-24 |
| 5717882 | Method and apparatus for dispatching and executing a load operation to memory | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland +2 more | 1998-02-10 |
| 5708843 | Method and apparatus for handling code segment violations in a computer system | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Rohit A. Vidwans | 1998-01-13 |
| 5694574 | Method and apparatus for performing load operations in a computer system | Jeffery M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland | 1997-12-02 |
| 5689674 | Method and apparatus for binding instructions to dispatch ports of a reservation station | James S. Griffith, Shantanu Gupta | 1997-11-18 |
| 5687338 | Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor | Darrell D. Boggs, Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Ashwani K. Gupta +1 more | 1997-11-11 |
| 5680572 | Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers | Haitham Akkary, Jeffrey M. Abramson, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland +2 more | 1997-10-21 |
| 5680565 | Method and apparatus for performing page table walks in a microprocessor capable of processing speculative instructions | Andy Glew, Haitham Akkary | 1997-10-21 |
| 5671444 | Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers | Haitham Akkary, Jeffrey M. Abramson, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland +2 more | 1997-09-23 |
| 5664137 | Method and apparatus for executing and dispatching store operations in a computer system | Jeffrey M. Abramson, Haitham Akkary, Atig A. Bajwa, Michael A. Fetterman, Andrew F. Glew +4 more | 1997-09-02 |
| 5627985 | Speculative and committed resource files in an out-of-order processor | Michael A. Fetterman, Andrew F. Glew, David B. Papworth, Robert P. Colwell | 1997-05-06 |
| 5623628 | Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue | James M. Brayton, Michael W. Rhodehamel, Nitin V. Sarangdhar | 1997-04-22 |
| 5615385 | Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming | Michael A. Fetterman, Andrew F. Glew, David B. Papworth, Robert P. Colwell | 1997-03-25 |
| 5613083 | Translation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructions | Andrew F. Glew, Haitham Akkary | 1997-03-18 |
| 5608885 | Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions | Ashwani K. Gupta, Chan Woo Lee | 1997-03-04 |
| 5606670 | Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system | Jeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Kris G. Konigsfeld, Paul D. Madland +1 more | 1997-02-25 |
| 5604753 | Method and apparatus for performing error correction on data from an external memory | John M. Bauer, Gregory P. Meece, David B. Papworth | 1997-02-18 |
| 5604878 | Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path | Robert P. Colwell, Michael A. Fetterman, Andrew F. Glew, Robert W. Martell, David B. Papworth | 1997-02-18 |
| 5604877 | Method and apparatus for resolving return from subroutine instructions in a computer processor | Bradley D. Hoyt, David B. Papworth, Ashwani K. Gupta, Michael A. Fetterman, Subramanian Natarajan +2 more | 1997-02-18 |