Issued Patents All Time
Showing 276–300 of 396 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9871106 | Heterogeneous pocket for tunneling field effect transistors (TFETs) | Uygar E. Avci, Roza Kotlyar, Benjamin Chu-Kung, Ian A. Young | 2018-01-16 |
| 9865684 | Nanoscale structure with epitaxial film having a recessed bottom portion | Benjamin Chu-Kung, Van H. Le, Robert S. Chau, Sansaptak Dasgupta, Niti Goel +8 more | 2018-01-09 |
| 9853107 | Selective epitaxially grown III-V materials based devices | Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Benjamin Chu-Kung, Marko Radosavljevic +3 more | 2017-12-26 |
| 9818847 | Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface | Robert S. Chau, Marko Radosavljevic, Han Wui Then, Scott B. Clendenning, Ravi Pillarisetty | 2017-11-14 |
| 9818870 | Transistor structure with variable clad/core dimension for stress and bandgap | Willy Rachmady, Van H. Le, Ravi Pillarisetty, Marko Radosavljevic, Niloy Mukherjee +4 more | 2017-11-14 |
| 9812574 | Techniques and configurations for stacking transistors of an integrated circuit device | Ravi Pillarisetty, Charles C. Kuo, Han Wui Then, Willy Rachmady, Van H. Le +3 more | 2017-11-07 |
| 9799759 | Techniques for forming non-planar germanium quantum well devices | Ravi Pillarisetty, Jack T. Kavalieros, Willy Rachmady, Uday Shah, Benjamin Chu-Kung +4 more | 2017-10-24 |
| 9768269 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Niloy Mukherjee, Matthew V. Metz, Jack T. Kavalieros, Nancy Zelick, Robert S. Chau | 2017-09-19 |
| 9748338 | Preventing isolation leakage in III-V devices | Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee | 2017-08-29 |
| 9698013 | Methods and structures to prevent sidewall defects during selective epitaxy | Niloy Mukherjee, Niti Goel, Sanaz K. Gardner, Pragyansri Pathi, Matthew V. Metz +6 more | 2017-07-04 |
| 9691857 | Group III-N nanowire transistors | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Jack T. Kavalieros, Matthew V. Metz +3 more | 2017-06-27 |
| 9685508 | High voltage field effect transistors | Han Wui Then, Robert S. Chau, Benjamin Chu-Kung, Jack T. Kavalieros, Matthew V. Metz +3 more | 2017-06-20 |
| 9685381 | Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon | Niti Goel, Ravi Pillarisetty, Willy Rachmady, Jack T. Kavalieros, Benjamin Chu-Kung +4 more | 2017-06-20 |
| 9666583 | Methods of containing defects for non-silicon device engineering | Niti Goel, Ravi Pillarisetty, Niloy Mukherjee, Robert S. Chau, Willy Rachmady +6 more | 2017-05-30 |
| 9666492 | CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture | Marko Radosavljevic, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Willy Rachmady +4 more | 2017-05-30 |
| 9653548 | Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack | Marko Radosavljevic, Ravi Pillarisetty, Benjamin Chu-Kung, Niloy Mukherjee | 2017-05-16 |
| 9653559 | Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same | Niloy Mukherjee, Marko Radosavljevic, Niti Goel, Sanaz Kabehie, Matthew V. Metz +1 more | 2017-05-16 |
| 9640671 | Deep gate-all-around semiconductor device having germanium or group III-V active layer | Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian +5 more | 2017-05-02 |
| 9640537 | Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy | Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz +7 more | 2017-05-02 |
| 9640622 | Selective epitaxially grown III-V materials based devices | Niti Goel, Niloy Mukherjee, Matthew V. Metz, Marko Radosavljevic, Benjamin Chu-Kung +2 more | 2017-05-02 |
| 9640646 | Semiconductor device having group III-V material active region and graded gate dielectric | Marko Radosavljevic, Ravi Pillarisetty, Matthew V. Metz | 2017-05-02 |
| 9634007 | Trench confined epitaxially grown device layer(s) | Ravi Pillarisetty, Seung Hoon Sung, Niti Goel, Jack T. Kavalieros, Sansaptak Dasgupta +7 more | 2017-04-25 |
| 9583602 | Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs | Roza Kotlyar, Stephen M. Cea, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios +4 more | 2017-02-28 |
| 9570614 | Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation | Ravi Pillarisetty, Sansaptak Dasgupta, Niti Goel, Van H. Le, Marko Radosavljevic +8 more | 2017-02-14 |
| 9564490 | Apparatus and methods for forming a modulation doped non-planar transistor | Ravi Pillarisetty, Mantu K. Hudait, Marko Radosavljevic, Willy Rachmady, Jack T. Kavalieros | 2017-02-07 |