Issued Patents All Time
Showing 301–325 of 378 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6970373 | Method and apparatus for improving stability of a 6T CMOS SRAM cell | Suman Datta, Robert S. Chau, Jack T. Kavalieros, Bo Zheng, Scott A. Hareland | 2005-11-29 |
| 6967140 | Quantum wire gate device and method of making same | — | 2005-11-22 |
| 6960517 | N-gate transistor | Rafael Rios, Thomas D. Linton, Jack T. Kavalieros | 2005-11-01 |
| 6953719 | Integrating n-type and p-type metal gate transistors | Mark L. Doczy, Justin K. Brask, Steven J. Keating, Chris Barns, Michael L. McSwiney +2 more | 2005-10-11 |
| 6952040 | Transistor structure and method of fabrication | Robert S. Chau, Jack T. Kavalieros, Anand S. Murthy, Brian Roberds | 2005-10-04 |
| 6949476 | Method of creating shielded structures to protect semiconductor devices | David B. Fraser | 2005-09-27 |
| 6914295 | Tri-gate devices and methods of fabrication | Robert S. Chau, Jack T. Kavalieros, Douglas Barlage, Suman Datta, Scott A. Hareland | 2005-07-05 |
| 6909151 | Nonplanar device with stress incorporation layer and method of fabrication | Scott A. Hareland, Robert S. Chau, Suman Datta, Been-Yih Jin | 2005-06-21 |
| 6887395 | Method of forming sub-micron-size structures over a substrate | Scott A. Hareland, Robert S. Chau | 2005-05-03 |
| 6858478 | Tri-gate devices and methods of fabrication | Robert S. Chau, Jack T. Kavalieros, Douglas Barlage, Suman Datta, Scott A. Hareland | 2005-02-22 |
| 6858483 | Integrating n-type and p-type metal gate transistors | Mark L. Doczy, Justin K. Brask, Steven J. Keating, Chris Barns, Michael L. McSwiney +2 more | 2005-02-22 |
| 6815310 | Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel | Brian Roberds | 2004-11-09 |
| 6794232 | Method of making MOSFET gate electrodes with tuned work function | Jun Zheng, Gang Bai, Chunlin Liang | 2004-09-21 |
| 6790704 | Method for capacitively coupling electronic devices | Quat Vu, David B. Fraser | 2004-09-14 |
| 6790731 | Method for tuning a work function for MOSFET gate electrodes | Jun Zheng, Gang Bai, Chunlin Liang | 2004-09-14 |
| 6784491 | MOS devices with reduced fringing capacitance | Jack T. Kavalieros | 2004-08-31 |
| 6744116 | Thin film using non-thermal techniques | — | 2004-06-01 |
| 6740913 | MOS transistor using mechanical stress to control short channel effects | Brian Roberds | 2004-05-25 |
| 6737710 | Transistor structure having silicide source/drain extensions | Peng Cheng, Gang Bai | 2004-05-18 |
| 6727549 | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer | — | 2004-04-27 |
| 6717213 | Creation of high mobility channels in thin-body SOI devices | Brian Roberds | 2004-04-06 |
| 6696369 | Method of creating shielded structures to protect semiconductor devices | David B. Fraser | 2004-02-24 |
| 6696345 | Metal-gate electrode for CMOS transistor applications | Robert S. Chau, Mark L. Doczy, Jack T. Kavalieros | 2004-02-24 |
| 6689702 | High dielectric constant metal oxide gate dielectrics | Gang Bai, David B. Fraser, Peng Cheng, Chunlin Liang | 2004-02-10 |
| 6664173 | Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control | Mark L. Doczy, Pat Stokley | 2003-12-16 |